MC68HC705C Motorola, MC68HC705C Datasheet - Page 22

• Manufacturer Part Number: MC68HC705C
• Description: HCMOS Microcontroller Unit
• Manufacturer: Motorola

General Description
1.5 Block Diagram
Technical Data
22
RAM0 — Random-Access Memory Control Bit 0
RAM1 — Random-Access Memory Control Bit 1
SEC — Security Bit
IRQ — Interrupt Request Pin Sensitivity Bit
Bits 5, 4, and 0 — Not used; always read 0
Bit 2 — Unaffected by reset; reads either 1 or 0
Figure 1-2
This bit is implemented as an erasable, programmable read-only
memory (EPROM) cell and is not affected by reset.
IRQ is set only by reset, but can be cleared by software. This bit can
be written only once.
1 = Maps 32 bytes of RAM into page zero starting at address
0 = Provides 48 bytes of PROM at location $0020–$005F.
1 = Maps 96 bytes of RAM into page one starting at address $0100.
0 = Provides 96 bytes of PROM at location $0100.
1 = Bootloader disabled; MCU operates only in single-chip mode
0 = Security off; bootloader can be enabled
1 = IRQ pin is both negative edge- and level-sensitive.
0 = IRQ pin is negative edge-sensitive only.
$0030. Addresses from $0020 to $002F are reserved. This bit
can be read or written at any time, allowing memory
configuration to be changed during program execution.
This bit can be read or written at any time, allowing memory
configuration to be changed during program execution.
shows the structure of the MC68HC705C8A.
General Description
MC68HC705C8A — Rev. 2.0
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