MC68HC705C Motorola, MC68HC705C Datasheet - Page 123

• Manufacturer Part Number: MC68HC705C
• Description: HCMOS Microcontroller Unit
• Manufacturer: Motorola

MC68HC705C8A — Rev. 2.0
MOTOROLA
$000D
$000E
$000F
$0010
$0011
Addr.
SCI Control Register 1
SCI Control Register 2
SCI Status Register
Baud Rate Register
SCI Data Register
Register Name
See page 134.
See page 128.
See page 129.
See page 131.
See page 127.
Figure 10-3. SCI Transmitter I/O Register Summary
(SCCR1)
(SCCR2)
(SCDR)
(SCSR)
(Baud)
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read: TDRE
Read:
Write:
Write:
Write:
Write:
Write:
Writing a logic 1 to the TE bit in SCI control register 2 (SCCR2)
and then writing data to the SCDR begins the transmission. At the
start of a transmission, transmitter control logic automatically
loads the transmit shift register with a preamble of logic 1s. After
the preamble shifts out, the control logic transfers the SCDR data
into the shift register. A logic 0 start bit automatically goes into the
least significant bit (LSB) position of the shift register, and a logic
1 stop bit goes into the most significant bit (MSB) position.
When the data in the SCDR transfers to the transmit shift register,
the transmit data register empty (TDRE) flag in the SCI status
register (SCSR) becomes set. The TDRE flag indicates that the
SCDR can accept new data from the internal data bus.
When the shift register is not transmitting a character, the
PD1/TDO pin goes to the idle condition, logic 1. If software clears
the TE bit during the idle condition, and while TDRE is set, the
transmitter relinquishes control of the PD1/TDO pin.
Serial Communications Interface (SCI)
Bit 7
Bit 7
TIE
R8
U
U
0
1
= Unimplemented
TCIE
Bit 6
TC
T8
U
U
6
0
1
RDRF
SCP1
Bit 5
RIE
5
0
0
0
U = Unaffected
SCP0
Unaffected by reset
IDLE
Bit 4
ILIE
M
U
4
0
0
0
Serial Communications Interface (SCI)
WAKE
Bit 3
OR
TE
U
U
3
0
0
SCR2
Bit 2
RE
NF
U
2
0
0
SCR1
RWU
Bit 1
Technical Data
SCI Operation
FE
U
1
0
0
SCR0
Bit 0
SBK
Bit 0
U
U
0
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