MC68HC705C Motorola, MC68HC705C Datasheet - Page 50

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MC68HC705C

Manufacturer Part Number
MC68HC705C
Description
HCMOS Microcontroller Unit
Manufacturer
Motorola
Datasheet

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Interrupts
Technical Data
50
CONNECTION
USED WITH
NORMALLY
WIRED-OR
b. Level-Sensitive Trigger Condition. If the interrupt line remains low after servicing an interrupt, then the
INTERRUPT PIN
a. Edge-Sensitive Trigger Condition. The minimum pulse width (t
CPU continues to recognize an interrupt.
or 250 ns (f
execute the interrupt service routine plus 19 t
IRQ PIN
(INTERNAL)
Figure 4-1. External Interrupt Internal Function Diagram
IRQ
IRQ
.
.
.
IRQ
OP
1
n
EDGE- AND LEVEL-SENSITIVE TRIGGER
= 1 MHz). The period t
V
DD
Figure 4-2. External Interrupt Timing
OPTION REGISTER
D
C
IRQ LATCH
t
ILIH
R
Q
Q
ILIL
should not be less than the number of t
t
ILIH
Interrupts
CYC
t
ILIL
cycles.
I BIT (CCR)
ILIH
) is either 125 ns (f
POR
INTERNAL RESET (COP)
EXTERNAL RESET
EXTERNAL INTERRUPT BEING SERVICED
(VECTOR FETCH)
EXTERNAL
INTERRUPT
REQUEST
CYC
MC68HC705C8A — Rev. 2.0
cycles it takes to
OP
= 2.1 MHz)
MOTOROLA

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