Z8S180 Zilog., Z8S180 Datasheet - Page 94

• Manufacturer Part Number: Z8S180
• Description: ENHANCED Z180 MICROPROCESSOR
• Manufacturer: Zilog.

Note:
The vector table address is located on 256 byte boundaries in the 64KB
logical address space programmed in the 8-bit Interrupt Vector Register
(1). Figure 39 depicts the INT0 Mode 2 Vector acquisition.
Figure 39.
During the INT0 Mode 2 acknowledge cycle, the low-order 8 bits of the
vector is fetched from the data bus at the rising edge of T3 and the CPU
acquires the 16-bit vector.
Next, the PC is stacked. Finally, the 16-bit restart address is fetched from
the vector table and execution begins at that address.
During RESET the Interrupt Vector Register (I) is initialized to
if necessary, should be set to a different value prior to the occurrence of a
Mode 2 INT0 interrupt. Figure illustrates INT0 interrupt Mode 2 Timing.
Interrupt Vector
Register I
External vector acquisition is indicated by both MI and IORQ
LOW. Two Wait States (TW) are automatically inserted for
external vector fetch cycles.
16-bit Vector
INT0 Mode 2 Vector Acquisition
Data Bus
8-bit on
Offset
Vector + 1
Vector
of starting address
of starting address
High-order 8 bits
Low-order 8 bits
Memory
M PU Us e r M anual
UM005001-ZMP0400
Z 8018x Fam il y
256 Bytes
Vector
Table
00H
and,
79