Z8S180 Zilog., Z8S180 Datasheet - Page 110

• Manufacturer Part Number: Z8S180
• Description: ENHANCED Z180 MICROPROCESSOR
• Manufacturer: Zilog.

DMA Status Register (DSTAT: 30H)
Bit
Bit/Field
R/W
Reset
Note: R = Read W = Write X = Indeterminate ? = Not Applicable
Bit
Position Bit/Field R/W
7
DE1
R/W
DE1
7
0
DMA Status Register (DSTAT)
DSTAT is used to enable and disable DMA transfer and DMA termination
interrupts. DSTAT also determines DMA transfer status, that is, completed
or in progress.
R/W
DE0
R/W
6
0
Value
DWE1
W
5
1
Description
Enable Channel 1 — When DE1 = 1 and DME = 1,
channel 1 DMA is enabled. When a DMA transfer
terminates (BCR1 = 0), DE1 is reset to 0 by the DMAC.
When DE1 = 0 and the DMA interrupt is enabled (DIE1 =
1), a DMA interrupt request is made to the CPU.
To perform a software write to DE1, DWE1 is written with
0 during the same register write access. Writing DE1 to 0
disables channel 1 DMA, but DMA is restartable. Writing
DE1 to 1 enables channel 1 DMA and automatically sets
DME (DMA Main Enable) to 1. DE1 is cleared to 0 during
RESET.
DWE0
W
4
1
DIE1
R/W
3
0
DIE0
R/W
2
0
M PU Us e r M anual
UM005001-ZMP0400
Z 8018x Fam il y
1
?
?
?
DME
R
0
9 5