Z8S180 Zilog., Z8S180 Datasheet - Page 84

• Manufacturer Part Number: Z8S180
• Description: ENHANCED Z180 MICROPROCESSOR
• Manufacturer: Zilog.

If IEF1 is
the DI (Disable Interrupts) instruction and set to
Interrupts) instruction.
The purpose of IEF2 is to correctly manage the occurrence of NMI.
During NMI, the prior interrupt reception state is saved and all maskable
interrupts are automatically disabled (IEF1 copied to IEF2 and then IEF1
cleared to
the RETN (Return from Non-maskable Interrupt) automatically restores
the interrupt receiving state (by copying IEF2 to IEF1) prior to the
occurrence of NMI.
Table 8 describes how the IEF2 state can be reflected in the P/V bit of the
CPU Status Register by executing LD A, I or LD A, R instructions.
Table 8.
CPU
Operation
RESET
NMI
RETN
Interrupt except
NMI end TRAP
RETI
TRAP
EI
0
0
, all maskable interrupts are disabled. IEF1 can be reset to
State of IEF1 and IEF2
). At the end of the NMI interrupt service routine, execution of
IEF1
0
0
IEF2
0
not affected not affected
not affected not affected
1
IEF2
0
IEF1
not affected Returns from the NMI service
0
1
REMARKS
Inhibits the interrupt except NMI
and TRAP.
Copies the contents of IEF1 to
IEF2
routine.
Inhibits the interrupt except NMI
end TRAP
1
M PU Us e r M anual
by the El (Enable
UM005001-ZMP0400
Z 8018x Fam il y
0
by
69