PF38F5070M0Y0T0 NUMONYX [Numonyx B.V], PF38F5070M0Y0T0 Datasheet - Page 51

• Manufacturer Part Number: PF38F5070M0Y0T0
• Description: Numonyx StrataFlash Wireless Memory
• Manufacturer: NUMONYX [Numonyx B.V]

Numonyx™ StrataFlash
11.3
11.3.1
November 2007
Order Number: 313295-04
If an attempt is made to program past an erase-block boundary using the Buffered
Program command, the device aborts the operation. This generates a command
sequence error, and Status Register bits SR[5,4] are set.
If Buffered programming is attempted while V
SR[4,3] are set. If any errors are detected that have set Status Register bits, the
Status Register should be cleared using the Clear Status Register command.
Buffered Enhanced Factory Programming
Buffered Enhanced Factory Programing (Buffered EFP) speeds up Multi-Level Cell (MLC)
flash programming for today's beat-rate-sensitive manufacturing environments. The
enhanced programming algorithm used in Buffered EFP eliminates traditional
programming elements that drive up overhead in device programmer systems.
Buffered EFP consists of three phases: Setup, Program/Verify, and Exit (see
“Buffered EFP Flowchart” on page
performance across 32 data words. Verification occurs in the same phase as
programming to accurately program the flash memory cell to the correct bit state.
A single command sequence is used to program a block of data. This enhancement
eliminates three write cycles per buffer: two commands and the word count for each
set of 32 data words. Host programmer bus cycles fill the device’s write buffer followed
by a status check. SR[0] indicates when data from the buffer has been programmed
into sequential flash memory array locations.
Following the buffer-to-flash array programming sequence, the Write State Machine
(WSM) increments internal addressing to automatically select the next 32-word array
boundary. This aspect of Buffered EFP saves host programming equipment the address-
bus setup overhead.
With adequate continuity testing, programming equipment can rely on the WSM’s
internal verification to ensure that the device has programmed properly. This eliminates
the external post-program verification and its associated overhead.
Buffered EFP Requirements and Considerations
Buffered EFP requirements:
Buffered EFP considerations:
• Ambient temperature: T
• V
• VPP driven to V
• Target block unlocked before issuing the Buffered EFP Setup and Confirm
• The first-word address (WA0) for the block to be programmed must be held
• WA0 must align with the start of an array buffer boundary
• For optimum performance, cycling must be limited below 100 erase cycles per
• Buffered EFP programs one block at a time; all buffer data must fall within a single
• Buffered EFP cannot be suspended.
• Programming to the flash memory array can occur only when the buffer is full
commands.
constant from the setup phase through all data streaming into the target block,
until transition to the exit phase is desired.
block
block
CC
®
Wireless Memory (L18 AD-Mux)
within specified operating range.
2
3
.
.
PPH
.
C
= 25°C, ±5°C
79). It uses a write buffer to spread MLC program
PP
is below V
PPLK
1
, Status Register bits
.
Figure 34,
Datasheet
4
.
51