PF38F5070M0Y0T0 NUMONYX [Numonyx B.V], PF38F5070M0Y0T0 Datasheet - Page 42

• Manufacturer Part Number: PF38F5070M0Y0T0
• Description: Numonyx StrataFlash Wireless Memory
• Manufacturer: NUMONYX [Numonyx B.V]

10.2.1
10.3
.
Table 19: Read Configuration Register Description (Sheet 1 of 2)
Datasheet
42
Read Configuration Register (RCR)
15
14
Mode
Read
RM
Bit
15
Read Mode (RM)
Reserved (R)
RES
14
R
“flow through” behavior only applies to the first access of any synchronous read bus
cycle. All subsequent data is driven on valid clock edges following the first access
latency; however, for a synchronous non-array read, the same word of data will be
output on successive clock edges until the burst length requirements are satisfied.
During synchronous read operations, after OE# is driven low WAIT indicates invalid
data on subsequent clock edges when asserted, and valid data when de-asserted with
respect to a valid clock edge. See
through Feature Timing” on page 26
for additional details. Synchronous burst reads are permitted in all blocks.
Burst Suspend
The Burst Suspend feature of the device can reduce or eliminate the initial access
latency incurred when system software needs to suspend a burst sequence that is in
progress in order to retrieve data from another device on the same system bus. The
system processor can resume the burst sequence later. Burst suspend provides
maximum benefit in non-cache systems.
Burst accesses can be suspended during the initial access latency (before data is
received) or after the device has output data. When a burst access is suspended,
internal array sensing continues and any previously latched internal data is retained. A
burst sequence can be suspended and resumed without limit as long as device
operation conditions are met.
Burst Suspend occurs when CE# is asserted, the current address has been latched
(either ADV# rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK
can be halted when it is at V
To resume the burst access, OE# is reasserted and CLK is restarted. Subsequent CLK
edges resume the burst sequence. See
Read Configuration Register (RCR)
The RCR is used to select the read mode (synchronous or asynchronous), and it defines
the synchronous burst characteristics of the device. To modify RCR settings, use the
Configure Read Configuration Register command (see
on page
RCR contents can be examined using the Read Device Identifier command, and then
reading from <partition base address> + 0x05 (see
Identifier” on page
The RCR is shown in
13
Latency Count
Name
LC[2:0]
12
37).
11
0 = Synchronous burst-mode read
1 = Asynchronous read (default)
Reserved bits should be cleared (0)
Polarity
WAIT
67).
WP
10
Table
Data
Hold
19. The following sections describe each RCR bit
DH
9
IH
or V
Delay
WAIT
WD
8
Figure 7, “Synchronous Array Read with Flow-
IL
.
and
Numonyx™ StrataFlash
Burst
Figure 9, “Burst Suspend Timing” on page
Seq
BS
7
Figure 9, “Burst Suspend Timing” on page 27
Edge
CLK
CE
6
Description
RES
Section 15.2, “Read Device
R
5
Section 9.2, “Device Commands”
®
RES
R
4
Wireless Memory (L18 AD-Mux)
Burst
Wrap
BW
3
Order Number: 313295-04
2
Burst Length
November 2007
BL[2:0]
1
27.
0