PF38F5070M0Y0T0 NUMONYX [Numonyx B.V], PF38F5070M0Y0T0 Datasheet - Page 13

• Manufacturer Part Number: PF38F5070M0Y0T0
• Description: Numonyx StrataFlash Wireless Memory
• Manufacturer: NUMONYX [Numonyx B.V]

Numonyx™ StrataFlash
4.1
Table 2:
November 2007
Order Number: 313295-04
Address and Data Signals, AD-Mux
A[MAX:16
]
DQ[15:0]
Control Signals
ADV#
F[3:1]-
CE#
CLK
F[2:1]-
OE#
R-OE#
F-RST#
Symbol
Input /
Output
Type
Input
Input
Input
Input
Input
Input
Input
Signal Descriptions (Sheet 1 of 3)
Signal Descriptions
ADDRESS: Global device signals.
Shared address inputs for all memory die during Read and Write operations.
ADDRESS-DATA MULTIPLEXED INPUTS/ OUTPUTS: AD-Mux I/O flash signals.
During AD-Mux Read cycles, DQ[15:0] are used to input the lower address followed by read-data
output. During AD-Mux Write cycles, DQ[15:0] are used to input the lower address followed by
commands or data.
ADDRESS VALID: Flash- and Synchronous PSRAM-specific signal; low-true input.
Note:
FLASH CHIP ENABLE: Flash-specific signal; low-true input.
When low, F-CE# selects the associated flash memory die. When high, F-CE# deselects the
associated flash die. Flash die power is reduced to standby levels, and its data and F-WAIT outputs
are placed in a High-Z state.
CLOCK: Flash- and Synchronous PSRAM-specific input signal.
CLK synchronizes the flash and/or synchronous PSRAM with the system clock during synchronous
operations.
FLASH OUTPUT ENABLE: Flash-specific signal; low-true input.
When low, F-OE# enables the output drivers of the selected flash die. When high, F-OE# disables
the output drivers of the selected flash die and places the output drivers in High-Z.
RAM OUTPUT ENABLE: PSRAM- and SRAM-specific signal; low-true input.
When low, R-OE# enables the output drivers of the selected memory die. When high, R-OE#
disables the output drivers of the selected memory die and places the output drivers in High-Z. If
device not present, treat as RFU.
FLASH RESET: Flash-specific signal; low-true input.
When low, F-RST# resets internal operations and inhibits writes. When high, F-RST# enables
normal operation.
• 256-Mbit: AMAX = A23
• 128-Mbit: AMAX = A22
• 64-Mbit: AMAX = A21
• A0 is the lowest-order word address.
• Unused address inputs should be treated as RFU.
• DQ[15:0] are High-Z when the device is deselected or its output is disabled.
• DQ[15:0] is only used with AD-Mux I/O flash device.
• During a synchronous flash Read operation, the address is latched on the rising edge of ADV#
• During synchronous PSRAM read and synchronous write modes, the address is either latched
• F1-CE# is dedicated to flash die #1.
• F[3:2]-CE# are dedicated to flash die #3 through #2, respectively, if present. Otherwise, any
• F2-OE# common to all other flash dies, if present. Otherwise it is an RFU, however, it is highly
®
or the first active CLK edge whichever occurs first. In an asynchronous flash Read operation,
the address is latched on the rising edge of ADV# or continuously flows through while ADV#
is low.
on the first rising clock edge after ADV# assertion or on the rising edge of ADV# whichever
edge comes first. In asynchronous read and asynchronous write modes, ADV# can be used to
latch the address, but can be held low for the entire operation as well.
unused flash chip enable should be treated as RFU.
recommended to always common F1-OE# and F2-OE# on the PCB.
Wireless Memory (L18 AD-Mux)
During A/D-Mux I/O operation, ADV# must remain deasserted during the data phase.
Signal Descriptions
Datasheet
1
2
Note
s
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