PF38F5070M0Y0T0 NUMONYX [Numonyx B.V], PF38F5070M0Y0T0 Datasheet - Page 33

• Manufacturer Part Number: PF38F5070M0Y0T0
• Description: Numonyx StrataFlash Wireless Memory
• Manufacturer: NUMONYX [Numonyx B.V]

Numonyx™ StrataFlash
8.0
8.1
8.2
November 2007
Order Number: 313295-04
Power and Reset Specifications
Power Up and Down
Power supply sequencing is not required if VCC, VCCQ, and VPP are connected
together. If VCCQ and/or VPP are not connected to the VCC supply, then V
attain V
supply voltage equals V
Power supply transitions should only occur when RST# is low. This
accidental programming or erasure during power transitions.
Reset
Asserting RST# during a system reset is important with automated program/erase
devices because systems typically expect to read from flash memory when coming out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
may not occur. This is because the flash memory may be providing status information,
instead of array data as expected. Connect RST# to the same active-low reset signal
used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
System designers should guard against spurious writes when V
V
either signal inhibits writes to the device.
The Command User Interface (CUI) architecture provides additional protection because
alteration of memory contents can only occur after successful completion of a two-step
command sequence (see
LKO
. Because both WE# and CE# must be asserted for a write operation, deasserting
®
Wireless Memory (L18 AD-Mux)
CCMIN before applying VCCQ and VPP.
CCMIN.
Section 9.2, “Device Commands” on page
Device inputs should not be driven before
protects the device from
CC
voltages are above
37).
CC
should
Datasheet
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