A25L05P AMICC [AMIC Technology], A25L05P Datasheet - Page 16

• Manufacturer Part Number: A25L05P
• Description: 2Mbit / 1Mbit / 512Kbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface
• Manufacturer: AMICC [AMIC Technology]

Table 7. Protection Modes
Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 1.
The protection features of the device are summarized in Table
7.
When the Status Register Write Disable (SRWD) bit of the
Status Register is 0 (its initial delivery state), it is possible to
write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction, regardless of the whether Write Protect
(
When the Status Register Write Disable (SRWD) bit of the
Status Register is set to 1, two cases need to be considered,
depending on the state of Write Protect (
­
­
(August, 2007, Version 1.0)
W
Signal
W
If Write Protect (
to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
If Write Protect (W) is driven Low, it is not possible to write
to the Status Register even if the Write Enable Latch
(WEL) bit has previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the Status
) is driven High or Low.
1
0
1
0
SRWD
Bit
0
0
1
1
W
Protected
Hardware
Protected
Software
(HPM)
(SPM)
Mode
) is driven High, it is possible to write
Status Register is Writable (if the
WREN instruction has set the
WEL bit) The values in the
SRWD, BP1 and BP0 bits can be
changed
Status Register is Hardware write
protected The values in the
SRWD, BP1 and BP0 bits cannot
be changed
Write Protection of the
W
Status Register
):
15
Regardless of the order of the two events, the Hardware
Protected Mode (HPM) can be entered:
­
­
The only way to exit the Hardware Protected Mode (HPM)
once entered is to pull Write Protect (
If Write Protect (
Protected Mode (HPM) can never be activated, and only the
Software Protected Mode (SPM), using the Block Protect
(BP1, BP0) bits of the Status Register, can be used.
Protected against Page
Program, Sector Erase
and Bulk Erase
Protected against Page
Program, Sector Erase
and Bulk Erase
Register are rejected, and are not accepted for execution).
As a consequence, all the data bytes in the memory area
that are software protected (SPM) by the Block Protect
(BP1, BP0) bits of the Status Register, are also hardware
protected against data modification.
by setting the Status Register Write Disable (SRWD) bit
after driving Write Protect (
or by driving Write Protect (
Status Register Write Disable (SRWD) bit.
A25L20P/A25L10P/A25L05P Series
Protected Area
W
) is permanently tied High, the Hardware
Memory Content
1
AMIC Technology Corp.
W
Ready to accept Page
Program and Sector Erase
instructions
Ready to accept Page
Program and Sector Erase
instructions
) Low
W
Unprotected Area
W
) Low after setting the
) High.
1