A25L05P AMICC [AMIC Technology], A25L05P Datasheet - Page 12

• Manufacturer Part Number: A25L05P
• Description: 2Mbit / 1Mbit / 512Kbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface
• Manufacturer: AMICC [AMIC Technology]

INSTRUCTIONS
All instructions, addresses and data are shifted in and out of
the device, most significant bit first.
Serial Data Input (DIO) is sampled on the first rising edge of
Serial Clock (C) after Chip Select (
one-byte instruction code must be shifted in to the device,
most significant bit first, on Serial Data Input (DIO), each bit
being latched on the rising edges of Serial Clock (C).
The instruction set is listed in Table 5.
Every instruction sequence starts with a one-byte instruction
code. Depending on the instruction, this might be followed by
address bytes, or by data bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at
Higher Speed (Fast_Read), Read Status Register (RDSR) or
Release from Deep Power-down, Read Device Identification
and Read Electronic Signature (RES) instruction, the shifted-in
instruction sequence is followed by a data-out sequence. Chip
Select (
Table 5. Instruction Set
Note: (1) DIO = (D
(August, 2007, Version 1.0)
WREN
WRDI
RDSR
WRSR
READ
FAST_READ
FAST_READ_DUAL
_OUTPUT
FAST_READ_DUAL
_INPUT-OUTPUT
PP
SE
BE
DP
RDID
RES
(2) Dual Input, DIO = (A22, A20, A18, ………, A6, A4, A2, A0)
Instruction
S
DO = (D
) can be driven High after any bit of the data-out
7
6
, D
, D
DO = (A23, A21, A19, …….., A7, A5, A3, A1)
5
4
, D
, D
Write Enable
Write Status Register
Read Data Bytes
Page Program
Write Disable
Read Status Register
Read Data Bytes at Higher Speed
Read Data Bytes at Higher Speed by
Dual Output
Read Data Bytes at Higher Speed by
Dual Input and Dual Output
Sector Erase
Bulk Erase
Deep Power-down
Read Device Identification
Release from Deep Power-down, and
Read Electronic Signature
Release from Deep Power-down
3
2
, D
, D
1
0
)
)
S
) is driven Low. Then, the
(1)
Description
(1)
11
sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Bulk
Erase (BE), Write Status Register (WRSR), Write Enable
(WREN), Write Disable (WRDI) or Deep Power-down (DP)
instruction, Chip Select (
byte boundary, otherwise the instruction is rejected, and is not
executed. That is, Chip Select (
number of clock pulses after Chip Select (
is an exact multiple of eight.
All attempts to access the memory array during a Write Status
Register cycle, Program cycle or Erase cycle are ignored, and
the internal Write Status Register cycle, Program cycle or
Erase cycle continues unaffected.
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 1011
0000 0010
1101 1000
1100 0111
1011 1001
1001 1111
1010 1011
00111011
10111011
Instruction Code
A25L20P/A25L10P/A25L05P Series
One-byte
0Bh
BBh
D8h
C7h
B9h
ABh
06h
04h
05h
01h
03h
3Bh
02h
9Fh
S
AMIC Technology Corp.
Address
) must be driven High exactly at a
Bytes
3
0
0
0
0
3
3
3
3
3
0
0
0
0
0
(2)
S
) must driven High when the
Dummy
Bytes
S
1
0
0
0
0
0
1
1
0
0
0
0
0
3
0
(2)
) being driven Low
1 to 256
Bytes
1 to ∞
1 to ∞
1 to ∞
1 to ∞
1 to ∞
1 to 4
Data
0
0
1
0
0
0
1
0