A25L05P AMICC [AMIC Technology], A25L05P Datasheet
A25L05P
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A25L05P Summary of contents
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... Revision History Rev. No. History 0.0 Initial issue 0.1 Add transient voltage (<20ns) on any pin to ground potential spec. 1.0 Final version release (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series With 85MHz SPI Bus Interface Issue Date February 13, 2007 April 24, 2007 August 9, 2007 Remark Preliminary Final AMIC Technology Corp. ...
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... With 85MHz SPI Bus Interface Top or Bottom boot block configuration available Electronic Signatures - JEDEC Standard Two-Byte Signature A25L20P: (2012h, Bottom) or (2022h, top) A25L10P: (2011h, Bottom) or (2021h, top) A25L05P: (2010h, Bottom) or (2020h, top) - RES Instruction, One-Byte, Signature, for backward compatibility A25L20P (11h) A25L10P (10h) A25L05P (05h) ...
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... Version 1.0) High Voltage Generator I/O Shift Register 256 Byte Data Buffer 3FFFh (2M), 1FFFh (1M), FFFh (512K) 00000h 256 Byte (Page Size) X Decoder Logic Symbol A25L20P/A25L10P/A25L05P Series Status Register Size of the read-only memory area 000FFh V CC DIO C A25L20P/ S A25L10P/ A25L05P W HOLD ...
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... For these two modes, input data is latched in on the rising edge of Serial Clock (C), and output data is available from the (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series Unless an internal Program, Erase or Write Status Register cycle is in progress, the device will be in the Standby mode (this is not the Deep Power-down mode) ...
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... CS2 CS1 W Note: The Write Protect ( ) and Hold ( Figure 2. SPI Modes Supported CPOL CPHA DIO DO (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series C DO DIO SPI Memory Device S W HOLD HOLD ) signals should be driven, High or Low as appropriate MSB DIO C DO ...
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... Write, Program or Erase instructions. (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series Status Register The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions. ...
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... Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP1, BP0) are 0. 2. A25L20P: The sector 3 include sector 3-0, sector 3-1, sector 3-2, sector 3-3 and sector 3-4. A25L10P: The sector 1 include sector 1-0, sector 1-1, sector 1-2, sector 1-3 and sector 1-4. A25L05P: The sector 0 include sector 0-0, sector 0-1, sector 0-2, sector 0-3 and sector 0-4. A25L20P/A25L10P/A25L05PU Bottom Boot Block Status Register Content ...
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... Figure 3. Hold Condition Activation C HOLD (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series Serial Clock (C) next goes Low. This is shown in Figure 3. During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DIO) and Serial Clock (C) are Don’t Care. ...
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... A25L20P Bottom Boot Block Address Table Sector 0-4 0-3 0-2 0-1 0-0 (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from but not Page Erasable. Sector Size (Kbytes ...
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... A25L10PU Bottom Boot Block Address Table Sector 1 0-4 0-3 0-2 0-1 0-0 (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from but not Page Erasable. Sector Size (Kbytes ...
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... Kbytes 256 pages (256 bytes each). Table 4. Memory Organization A25L05PT Top Boot Block Address Table Sector A25L05PU Bottom Boot Block Address Table Sector 0-4 0-3 0-2 0-1 0-0 (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable (bits are erased from but not Page Erasable ...
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... Dual Input, DIO = (A22, A20, A18, ………, A6, A4, A2, A0 (A23, A21, A19, …….., A7, A5, A3, A1) (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series sequence is being shifted out. In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP driven Low ...
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... Low, sending the instruction code, and then driving Chip The Write Enable Latch (WEL) bit is reset under the following conditions: Figure 5. Write Disable (WRDI) Instruction Sequence (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series The Write Enable (WREN) instruction is entered by driving Chip Select ( driving Chip Select ( S ...
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... Status Register (WRSR) instruction is no longer accepted for execution Instruction Status Register Out MSB 13 A25L20P/A25L10P/A25L05P Series W ) signal allow the device to be put in the Hardware Status Register Out MSB AMIC Technology Corp signal ...
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... C DIO DO (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. ...
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... Status Register even if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction. (Attempts to write to the Status (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series Write Protection of the Status Register Protected against Page Program, Sector Erase and Bulk Erase ...
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... DO Note: Address bits A23 to A18 are Don’t Care, for A25L20P. Address bits A23 to A17 are Don’t Care, for A25L10P. Address bits A23 to A16 are Don’t Care, for A25L05P (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series therefore, be read with a single Read Data Bytes (READ Low ...
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... Note: Address bits A23 to A18 are Don’t Care, for A25L20P. Address bits A23 to A17 are Don’t Care, for A25L10P. Address bits A23 to A16 are Don’t Care, for A25L05P (August, 2007, Version 1.0) Speed (FAST_READ) instruction. When the highest address S ) Low ...
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... DO Note: Address bits A23 to A18 are Don’t Care, for A25L20P. Address bits A23 to A17 are Don’t Care, for A25L10P. Address bits A23 to A16 are Don’t Care, for A25L05P (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series accomplished by adding eight “dummy” clocks after the 24-bit address as shown in figure 10. The dummy clocks allow the device’ ...
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... DIO DO Note: Address bits A23 to A18 are Don’t Care, for A25L20P. Address bits A23 to A17 are Don’t Care, for A25L10P. Address bits A23 to A16 are Don’t Care, for A25L05P (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series frequency accomplished by adding four “dummy” clocks after the 24-bit address as shown in figure 11 ...
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... Note: Address bits A23 to A18 are Don’t Care, for A25L20P. Address bits A23 to A17 are Don’t Care, for A25L10P. Address bits A23 to A16 are Don’t Care, for A25L05P (August, 2007, Version 1.0) programmed correctly within the same page. If less than 256 ...
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... DIO Note: Address bits A23 to A18 are Don’t Care, for A25L20P. Address bits A23 to A17 are Don’t Care, for A25L10P. Address bits A23 to A16 are Don’t Care, for A25L05P (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series instruction is not executed. As soon as Chip Select ( ...
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... Protect (BP1, BP0) bits are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected Instruction Address bits A23 to A17 are Don’t Care, for A25L10P. Address bits A23 to A16 are Don’t Care, for A25L05P AMIC Technology Corp driven High, ...
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... Figure 15. Deep Power-down (DP) Instruction Sequence DIO (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series The Deep Power-down mode automatically stops at Power-down, and the device always Powers-up in the Standby mode. The Deep Power-down (DP) instruction is entered by driving Chip Select ( Serial Data Input (DIO). Chip Select ( for the entire duration of the sequence ...
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... A25L20P, 21h(Top) or 11h(Bottom) for A25L10P, 20h(Top) or 10h(Bottom) for A25L05P). Any Read Identification (RDID) instruction while an Erase, or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress ...
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... C Instruction DIO High Impedance DO Note: The value of the 8-bit Electronic Signature, for the A25L20P is 11h, A25L10P is 10h, and A25L05P is 05h. (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series edge of Serial Clock (C). Then, the 8-bit Electronic Signature, and Read stored in the memory, is shifted out on Serial Data Output (DO), each bit being shifted out during the falling edge of Serial Clock (C) ...
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... Figure 18.), still insures that the device is put into Stand-by Power mode. If the device was not pre- viously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series t RES1 Instruction ...
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... Write Status Register, Program or Erase instructions should be sent until the later of: Figure 19. Power-up Timing V V (max (min) CC (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series t These values are specified in Table 9. If the delay VSL CC even if the t At Power-up, the device is in the following state: ...
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... Note: These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series Parameter 28 Min. Max. ...
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... Input Capacitance (other pins) IN Note: Sampled only, not 100% tested (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series *Comments Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of ...
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... Page Program Cycle Time PP t Sector Erase Cycle Time SE Bulk Erase Cycle Time of A25L20P t Bulk Erase Cycle Time of A25L10P BE Bulk Erase Cycle Time of A25L05P Note ° This is preliminary data Table 15. AC Measurement Conditions Symbol C Load Capacitance L Input Rise and Fall Times ...
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... Figure 20. AC Measurement I/O Waveform 0.8V 0.2V (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series Input Levels Input and Output Timing Reference Levels 0.7V CC 0.5V CC 0.3V CC AMIC Technology Corp. ...
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... Sector Erase Cycle Time SE Bulk Erase Cycle Time of A25L20P t Bulk Erase Cycle Time of A25L10P BE Bulk Erase Cycle Time of A25L05P Note must be greater than or equal Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. ...
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... Figure 21. Serial Input Timing S tCHSL C tDVCH DIO DO Figure 22. Write Protect Setup and Hold Timing during WRSR when SRWD=1 W tWHSL S C DIO DO (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series tSLCH tCHDX MSB IN High Impedance High Impedance 33 tSHSL tSHCH tCHSH tCHCL tCLCH LSB IN tSHWL AMIC Technology Corp. ...
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... Hold Timing Figure 23 DIO DO HOLD Figure 24. Output Timing S C DIO ADDR.LSB IN tCLQV tCLQX tCLQX DO (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series tHLCH tCHHL tCHHH tHLQZ tCH tCLQV 34 tHHCH tHHQX tCL tSHQZ LSB OUT tQLQH tQHQL AMIC Technology Corp. ...
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... Part Numbering Scheme * Optional (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series Package Material Blank: normal F: PB free Temperature* Package M = 209 mil SOP 150 mil SOP QFN 8 Boot Sector T = Top type U = Bottom type Device Version* Device Function P = Page Program & Sector Erase ...
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... A25L20PTM-F A25L20PTM-UF A25L20PTQ-F A25L20PTQ-UF A25L20PU-F A25L20PU-UF A25L20PUO-F A25L20PUO-UF 85 A25L20PUM-F A25L20PUM-UF A25L20PUQ-F A25L20PUQ- for industrial operating temperature range: -40 ° +85 ° C (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series Active Read Program/Erase Current Current Typ. (mA) Typ. (mA Standby Current Package Typ. (μA) ...
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... A25L10PTM-F A25L10PTM-UF A25L10PTQ-F A25L10PTQ-UF A25L10PU-F A25L10PU-UF A25L10PUO-F A25L10PUO-UF 85 A25L10PUM-F A25L10PUM-UF A25L10PUQ-F A25L10PUQ- for industrial operating temperature range: -40°C ~ +85°C (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series Active Read Program/Erase Current Current Typ. (mA) Typ. (mA Standby Current Package Typ. (μA) 8 Pin Pb-Free DIP (300 mil) ...
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... A25L05PTM-F A25L05PTM-UF A25L05PTQ-F A25L05PTQ-UF A25L05PU-F A25L05PU-UF A25L05PUO-F A25L05PUO-UF 85 A25L05PUM-F A25L05PUM-UF A25L05PUQ-F A25L05PUQ- for industrial operating temperature range: -40 ° +85 ° C (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series Active Read Program/Erase Current Current Typ. (mA) Typ. (mA Standby Current Package Typ. (μA) ...
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... Package Information P-DIP 8L Outline Dimensions Symbol Notes: 1. Dimension D and E 2. Dimension B 3. Tolerance: ± 0.010” (0.25mm) unless otherwise specified. (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series Dimensions in inches Min Nom Max 0.180 A 0.015 - - 0. 0.128 0.130 0.136 3. 0.014 0.018 0.022 0.36 B 0.050 ...
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... Package Information SOP 8L (150mil) Outline Dimensions e D (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series b ° 8 ° Dimensions in mm Symbol A 1.35~1.75 A 0.10~0. 0.33~0.51 D 4.7~5.0 E 3.80~4.00 e 1.27 BSC H 5.80~6. 0.40~1.27 Notes: 1. Maximum allowable mold flash is 0.15mm. 2. Complies with JEDEC publication 95 MS –012 AA. 3. All linear dimensions are in millimeters (max/min). ...
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... Package Information SOP 8L (209mil) Outline Dimensions (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series GAGE PLANE SEATING PLANE b Dimensions in mm Symbol Min Nom A 1.75 1.95 A 0.05 0. 1.70 1. 0.35 0.42 C 0.19 0.20 D 5.23 5.13 E 7.70 7.90 E 5.18 5. 1.27 BSC L 0.50 0.65 θ 0° - Notes: Maximum allowable mold flash is 0.15mm at the package ends and 0.25mm between leads ...
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... Package Information QFN 0.8mm) Outline Dimensions 4 5 Seating Plane (August, 2007, Version 1.0) A25L20P/A25L10P/A25L05P Series 1 0.25 C Pin1 ID Area 0. Dimensions in mm Symbol Min Nom Max Min A 0.700 0.750 0.800 27.6 A 0.000 0.020 0.050 0 0.203 REF 3 b 0.350 0.400 0.480 13 ...