ch7012a Chrontel, ch7012a Datasheet - Page 8

• Manufacturer Part Number: ch7012a
• Description: Ch7012 Tv Output Device
• Manufacturer: Chrontel

CHRONTEL
5. I
Two distinct methods of transferring data to the CH7012 are described. They are:
For the multiplexed data, clock at 1X pixel rate the data applied to the CH7012 is latched with both edges of
the clock (also referred to as dual-edge transfer mode). For the multiplexed data, clock at 2X pixel rate the data
applied to the CH7012 is latched with one edge of the clock. The polarity of the pixel clock can be reversed
under
5.1 Input Clock and Data Timing Diagram
The figure below shows the timing diagram for input data and clocks. The first XCLK/XCLK* waveform
represents the input clock for the multiplexed data, clock at 2X pixel rate method. The second XCLK/XCLK*
waveform represents the input clock for the multiplexed data, clock at 1X pixel rate method.
8
XCLK
/ XCLK
*
XCLK
/ XCLK
*
D[11:0]
DE
H
V
• Multiplexed data, clock input at 1X pixel rate
• Multiplexed data, clock input at 2X pixel rate
NPUT
serial port
I
NTERFACE
control.
Figure 4: Interface Timing
1 VGA Line
64 P-OUT
201-0000-042 Rev 2.1, 10/20/2004
CH7012A