ch7012a Chrontel, ch7012a Datasheet - Page 29

• Manufacturer Part Number: ch7012a
• Description: Ch7012 Tv Output Device
• Manufacturer: Chrontel

CHRONTEL
Bit 1 of register TPC should be left at the default value.
Bits 4-2 of register TPC contain the MSB values for the TV PLL divider ratio’s. These controls are described in
detail in the PLLM and PLLN register descriptions.
Bit 5 of register TPC controls the input latch bias current.
Bits 7-6 of register TPC control the memory sense amp reference level. The default value is recommended.
TV PLL M Value Register
Register PLLM controls the division factor applied to the 14.31818MHz frequency reference clock before it is input
to the TV PLL phase detector when the CH7012 is operating in master clock mode. The entire bit field, M[8:0], is
comprised of this register M[7:0] plus the MSB value contained in the TV PLL Control register, bit M8. In slave
clock mode, an external pixel clock is used instead of the 14.31818MHz frequency reference, and the division factor
is determined by the XCM value in register 1Dh. A table of values versus display mode is given following the
PLLN register description.
TV PLL N Value Register
Register PLLN controls the division factor applied to the VCO output before being applied to the PLL phase
detector, when the CH7012 is operating in master clock mode. The entire bit field, N[9:0], is comprised of this
register N[7:0] plus the MSB values contained in the TV PLL Control register, bits N9 and N8. In slave clock mode,
the value of ‘N’ is internally set to 1. The pixel clock generated in master clock modes is calculated according to the
equation Fpixel = Fref * [(N+2) / (M+2)]. When using a 14.31818MHz frequency reference, the required M and N
values for each mode are shown in Table 15 below:
201-0000-042 Rev 2.1, 10/20/2004
Table 14. PLLCAP setting vs Display Mode
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
TYPE:
TYPE:
11
12
13
14
15
16
17
18
19
BIT:
BIT:
R/W
R/W
M7
N7
7
0
7
0
1
0
1
1
1
0
0
0
0
R/W
R/W
M6
N6
6
0
6
1
31
32
33
34
35
36
37
38
R/W
R/W
M5
N5
5
1
5
1
R/W
R/W
1
1
1
0
0
0
1
1
M4
N4
4
1
4
1
R/W
R/W
M3
N3
3
1
3
1
R/W
R/W
M2
N2
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
2
1
2
1
R/W
R/W
M1
N1
CH7012A
1
1
1
1
PLLM
0Ah
8
PLLN
0Bh
8
R/W
R/W
M0
N0
29
0
1
0
0