ch7012a Chrontel, ch7012a Datasheet - Page 33

• Manufacturer Part Number: ch7012a
• Description: Ch7012 Tv Output Device
• Manufacturer: Chrontel

CHRONTEL
Bit 1 of register CM controls the P-Out clock frequency. A value of ‘0’ generates a clock output at the pixel
frequency, while a value of ‘1’ generates a clock at twice the pixel frequency.
Bit 2 of register CM controls the phase of the XCLK clock input to the CH7012. A value of ‘1’ inverts the XCLK
signal at the input of the device. This control is used to select which edge of the XCLK signal to use for latching
input data.
Bit 3 of register CM controls whether the device operates in master or slave clock mode. In master mode (M/S* =
‘1’), the 14.31818MHz clock is used as a frequency reference in the TV PLL, and the M and N values are used to
determine the TV PLL’s operating frequency. In slave mode (M/S* = ‘0’) the XCLK input is used as a reference to
the TV PLL. The M and N TV PLL divider values are forced to one.
Input Clock Register
Bits 3-0 of register IC controls the delay applied to the XCLK signal before latching input data.
GPIO Control Register
Bit 0 of register GPIO controls the polarity of the P-Out signal. A value of ‘0’ does not invert the clock at the output
pad.
Bit 1 of register GPIO enables the P-Out signal. A value of ‘1’ drives the P-Out clock signal out of the
P-Out pin. A value of ‘0’ disables the P-Out signal.
Bits 5-4 of register GPIO control the GPIO pins. When the corresponding GOENB bits are low, these register
values are driven out of the corresponding GPIO pins. When the corresponding GOENB bits are high, these register
values can be read to determine the level forced into the corresponding GPIO pins.
Bits 7-6 of register GPIO control the direction of the GPIO pins. A value of ‘1’ sets the corresponding GPIO pin to
an input, and a value of ‘0’ sets the corresponding pin to an output.
201-0000-042 Rev 2.1, 10/20/2004
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
TYPE:
TYPE:
BIT:
BIT:
GOENB1 GOENB0 GPIOL1 GPIOL0 Reserved Reserved
R/W
R/W
7
1
7
1
R/W
R/W
6
0
6
1
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
XCMD3 XCMD2 XCMD1
R/W
R/W
3
1
3
0
R/W
R/W
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
2
0
2
0
POUTE
R/W
R/W
CH7012A
1
0
1
0
IC
1Dh
8
GPIO
1Eh
8
XCMD0
POUTP
R/W
R/W
33
0
0
0
0