ch7012a Chrontel, ch7012a Datasheet - Page 41

• Manufacturer Part Number: ch7012a
• Description: Ch7012 Tv Output Device
• Manufacturer: Chrontel

CHRONTEL
8.2 Clock - Master, Sync - Slave Mode
201-0000-042 Rev 2.1, 10/20/2004
Table 28. Timing for Clock - Master, Sync - Slave Mode
Symbol
t1
t2
t3
t4
t5
P-OUT
XCLK
XCLK*
D[11:0]
H
V
DE
Parameter
P-OUT rise/fall time w/15pF load, VREF = 1.65 V
XCLK & XCLK* rise/fall time w/15pF load
Setup time:
Differential Clock: (XCLK = XCLK*) to (D[11:0], H, V & DE = VREF)
Single-ended Clock: (XCLK =VREF) to (D[11:0], H, V & DE = VREF)
Hold time:
Differential Clock: (XCLK = XCLK*) to (D[11:0], H, V & DE = VREF)
Single-ended Clock: (XCLK =VREF) to (D[11:0], H, V & DE = VREF)
D[11:0], H, V & DE rise/fall time w/15pF load
V
V
V
V
V
V
V
V
V
V
V
V
V
V
OH
OL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
IH
IL
Figure 18: Timing for Clock - Slave, Sync - Slave Mode
t5
64 PIXELS
t3
1 VGA
Line
t4
t5
t2
Min
0.5
0.5
t1
P0a
t3
Typ
P0b
3
3
3
t3
t1
P1a
P1b
Max
CH7012A
t4
P2a
P2b
t5
Unit
ns
ns
ns
ns
ns
41