ch7012a Chrontel, ch7012a Datasheet - Page 4

• Manufacturer Part Number: ch7012a
• Description: Ch7012 Tv Output Device
• Manufacturer: Chrontel

CHRONTEL
4
Table 1. Pin Description
64-Pin
LQFP
36
37
38
39
42
43
46
47
48
50 – 55,
58 – 63
# Pins
1
1
1
1
1
1
1
1
1
12
Type
Out
Out
Out
Out
In
In
Out
Out
Out
In
Symbol
CVBS
Y/G
C/R
CVBS/B
XI / FIN
XO
P-OUT
BCO/
V SYNC
C/H SYNC
D[11] - D[0]
Description
Composite Video
This pin outputs a composite video signal capable of driving a
75 ohm doubly terminated load.
Luma / Green Output
This pin outputs a selectable video signal.
designed to drive a 75 ohm doubly terminated load. The output
can be selected to be s-video luminance or green .
Chroma / Red Output
This pin outputs a selectable video signal. The output is
designed to drive a 75 ohm doubly terminated load. The output
can be selected to be s-video chrominance or red.
Composite Video / Blue Output
This pin outputs a selectable video signal. The output is
designed to drive a 75 ohm doubly terminated load. The output
can be selected to be composite video or blue.
Crystal Input / External Reference Input
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should
be attached between this pin and XO. However, an external
clock can drive the XI/FIN input.
Crystal Output
A parallel resonance 14.31818MHz crystal (+ 20 ppm) should
be attached between this pin and XI / FIN. However, if an
external CMOS clock is attached to XI/FIN, XO should be left
open.
Pixel Clock Output
When the CH7012 is operating as a VGA to TV encoder in
master clock mode, this pin provides a pixel clock signal to the
VGA controller which is used as a reference frequency. The
output is selectable between 1X or 2X of the pixel clock
frequency. The output driver is driven from the DVDDV
supply. This output has a programmable tri-state. The
capacitive loading on this pin should be kept to a minimum.
Buffered Clock Output / Vertical Sync Output
This output pin provides a buffered clock output, driven by the
DVDD supply. The output clock can be selected using the BCO
register.
Composite / Horizontal Sync Output
This pin can be selected to output a TV composite sync, TV
horizontal sync, or a buffered version of the VGA horizontal
sync. The output is driven from the DVDD supply.
Data[11] through Data[0] Inputs
These pins accept the 12 data inputs from a digital video port
of a graphics controller. The levels are 0 to DVDDV, and the
VREF signal is used as the threshold level.
201-0000-042 Rev 2.1, 10/20/2004
CH7012A
The output is