ch7012a Chrontel, ch7012a Datasheet - Page 34

• Manufacturer Part Number: ch7012a
• Description: Ch7012 Tv Output Device
• Manufacturer: Chrontel

CHRONTEL
Input Data Format Register
Bits 2-0 of register IDF select the input data format. See the Input interface on page 9 for a listing of available
formats.
Bit 3 of register IDF controls the horizontal sync polarity. A value of ‘0’ defines the horizontal sync to be active
low, and a value of ‘1’ defines the horizontal sync to be active high.
Bit 4 of register IDF controls the vertical sync polarity. A value of ‘0’ defines the vertical sync to be active low, and
a value of ‘1’ defines the vertical sync to be active high.
Bit 5 of register IDF controls the sync direction. A value of ‘0’ defines sync to be input to the CH7012, and a value
of ‘1’ defines sync to be output from the CH7012. The CH7012 can only output sync signals when operating as a
VGA to TV encoder.
Bit 6 of register IDF signifies when the CH7012 is to decode embedded sync signals present in the input data stream
instead of using the H and V pins. This feature is only available for input data format four. A value of ‘0’ selects the
H and V pins to be used as the sync inputs, and a value of ‘1’ selects the embedded sync signal.
Bit 7 of register IDF selects the input buffer used for the data, sync and clock input pins.
Connection Detect Register
The Connection Detect Register provides a means to sense the connection of a TV to the four DAC outputs. The status
bits, DACT[3:0] correspond to the termination of the four DAC outputs. However, the values contained in these STATUS
BITS ARE NOT VALID until a sensing procedure is performed. Use of this register requires a sequence of events to
enable the sensing of outputs, then reading out the applicable status bits. The detection sequence works as follows:
1) Set the power management register to enable all DAC’s.
2) Set the SENSE bit to a 1. This forces a constant output from the DAC’s. Note that during SENSE = 1, these 4 analog
outputs are at steady state and no TV synchronization pulses are asserted.
3) Reset the SENSE bit to 0. This triggers a comparison between the voltage present on these analog outputs and the
reference value. During this step, each of the four status bits corresponding to individual DAC outputs will be set if they
are CONNECTED.
4) Read the status bits. The status bits, DACT[3:0] now contain valid information which can be read to determine which
outputs are connected to a TV. Again, a “1” indicates a valid connection, a “0” indicates an unconnected output.
34
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
TYPE:
TYPE:
BIT:
BIT:
Reserved Reserved Reserved
R/W
R/W
IBS
7
0
7
0
DES
R/W
R/W
6
0
6
0
SYO
R/W
R
5
0
5
0
DACT3
R/W
VSP
X
R
4
0
4
DACT2
R/W
HSP
X
R
3
0
3
201-0000-042 Rev 2.1, 10/20/2004
DACT1
IDF2
R/W
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
X
R
2
0
2
DACT0
IDF1
R/W
CH7012A
X
R
1
0
1
CD
IDF
1Fh
8
20h
5
SENSE
IDF0
R/W
R/W
0
0
0
0