ch7012a Chrontel, ch7012a Datasheet - Page 26

• Manufacturer Part Number: ch7012a
• Description: Ch7012 Tv Output Device
• Manufacturer: Chrontel

CHRONTEL
Bit 6 of register CVBWB controls whether the chroma sub-carrier free-runs, or is locked to the video signal. A ‘1’ causes
the sub-carrier to lock to the TV vertical rate, and should be used when the CIVEN bit (register 10h) is set to ‘0’. A ‘0’
causes the sub-carrier to free-run, and should be used when the CIVEN bit is set to ‘1’.
Bit 7 of register CVBWB controls the vertical blanking interval defeat function. A ‘1’ in this register location forces the
flicker filter to minimum filtering during the vertical blanking interval. A ‘0’ in this location causes the flicker filter to
remain at the same setting inside and outside of the vertical blanking interval.
Text Enhancement Register
Bits 2-0 of register TE control the text enhancement circuitry within the CH7012. A value of ‘000’ minimizes the
enhancement feature, while a value of ‘111’ maximizes the enhancement.
Bits 5-3 of register TE contain the MSB values for the start of active video, horizontal position and vertical position
controls. They are described in detail in the SAV, HP and VP register descriptions.
Start of Active Video Register
Register SAV controls the delay, in pixel increments, from leading edge of horizontal sync to start of active video.
The entire bit field SAV[8:0] is comprised of this register SAV[7:0], plus the MSB value contained in the Text
Enhancement register, bit SAV8. This is decoded as a whole number of pixels, which can be set anywhere between
0 and 511 pixels. Therefore, in any 2X clock mode the number of 2X clocks from the leading edge of sync to the
first active data must be a multiple of two clocks.
Horizontal Position Register
Register HP is used to shift the displayed TV image in a horizontal direction (left or right) to achieve a horizontally
centered image on screen. The entire bit field, HP[8:0], is comprised of this register HP[7:0] plus the MSB value
contained in the Text Enhancement register, bit HP8. Increasing values move the displayed image position right, and
decreasing values move the image position left.
26
DEFAULT:
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
SYMBOL:
TYPE:
TYPE:
TYPE:
BIT:
BIT:
BIT:
SAV7
R/W
R/W
HP7
7
0
7
7
0
SAV6
R/W
R/W
HP6
6
1
6
6
1
SAV5
SAV8
R/W
R/W
R/W
HP5
5
0
5
0
5
0
SAV4
R/W
R/W
R/W
HP8
HP4
4
1
4
0
4
1
SAV3
R/W
R/W
R/W
VP8
HP3
3
0
3
0
3
0
201-0000-042 Rev 2.1, 10/20/2004
SAV2
R/W
R/W
R/W
HP2
TE2
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
2
0
2
1
2
0
SAV1
R/W
R/W
R/W
HP1
TE1
CH7012A
1
0
1
0
1
0
SAV
TE
03h
6
04h
8
HP
05h
8
SAV0
R/W
R/W
R/W
TE0
HP0
0
0
0
1
0
0