ch7012a Chrontel, ch7012a Datasheet - Page 36

• Manufacturer Part Number: ch7012a
• Description: Ch7012 Tv Output Device
• Manufacturer: Chrontel

CHRONTEL
Test Pattern Register
Bits 1-0 of register TSTP control the test pattern generation block. The pattern generated is determined by Table 21
below.
Bit 2 of register TSTP is a test control, and should be left at the default value.
Bit 3 of register TSTP controls the datapath reset signal. A value of ‘0’ holds the datapath in a reset condition,
while a value of ‘1’, places the datapath in normal mode. The datapath is also reset at power on by an internally
generated power on reset signal.
Bit 4 of register TSTP controls the serial port reset signal. A value of ‘0’ holds the serial port registers in a reset
condition, while a value of ‘1’, places the serial port registers in normal mode. The serial port registers are also reset
at power on by an internally generated power on reset signal.
Power Management Register
Register PM controls which circuitry within the CH7012 is operating, according to Table 22 below.
36
Table 20. K3 Selection
Table 21. Test Pattern Control
SHF[2:0]
000
001
010
011
100
101
110
111
TSTP[1:0]
00
01
1X
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
TYPE:
TYPE:
BIT:
BIT:
Reserved Reserved
K3
2.5
3.0
3.5
4.0
4.5
5.0
6.0
7.0
Test Pattern
No test pattern – Input data is used
Color Bars
Horizontal Luminance Ramp
R/W
7
7
0
R/W
6
6
0
R/W
TV DACPD3 DACPD2 DACPD1 DACPD0
5
5
0
ResetIB ResetDB
R/W
R/W
4
1
4
0
R/W
R/W
3
1
3
0
201-0000-042 Rev 2.1, 10/20/2004
RSA
R/W
R/W
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
2
0
2
0
TSTP1
R/W
R/W
CH7012A
1
0
1
0
TSTP
48h
5
PM
49h
8
TSTP0
R/W
R/W
FPD
0
0
0
1