p4c163-25pmlf Pyramid Semiconductor Corporation, p4c163-25pmlf Datasheet
p4c163-25pmlf
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p4c163-25pmlf Summary of contents
Page 1
... CMOS is used to reduce power consumption in both active and standby modes. The P4C163 and P4C163L are available in 28-pin 300 mil DIP and SOJ, 28-pin 350 x 550 mil LCC, and 28-pin CERPACK packages providing excellent board level densi- ties ...
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... This parameter is sampled and not 100% tested. Parameter Value Temperature Under –55 to +125 Bias Storage Temperature –65 to +150 Power Dissipation 1.0 DC Output Current 50 Ambient GND Temperature 0°C to +70°C 0V 5.0V ± 10% P4C163 P4C163L Min Max Min Max 2.2 V +0.5 2 –0.5 (3) 0.8 –0.5 (3) 0.8 V – ...
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... CC Current – 35 Standby Power Supply SB Current (TTL Input Levels Standby Power Supply SB1 Current (CMOS Input Levels) n/a = Not Applicable DATA RETENTION CHARACTERISTICS (P4C163L, Military Temperature Only) Symbol Parameter V V for Data Retention Data Retention Current CCDR t Chip Deselect to ...
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... P4C163/163L AC ELECTRICAL CHARACTERISTICS—READ CYCLE ( ± 10%, All Temperature Ranges) CC Symbol Parameter t Read Cycle Time RC t Address Access Time AA t Chip Enable AC Access Time t Output Hold from OH Address Change t Chip Enable to LZ Output in Low Z t Chip Disable to HZ Output in High Z t Output Enable ...
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... READ CYCLE NO Notes: 9. READ Cycle Time is measured from the last valid address to the first transitioning address. Document # SRAM120 REV C (5,6) CONTROLLED) (5,7,10) 2 10. Transitions caused by a chip enable control have similar delays irrespective of whether CE P4C163/163L or CE causes them Page ...
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... P4C163/163L AC CHARACTERISTICS—WRITE CYCLE ( ± 10%, All Temperature Ranges) CC Symbol Parameter t Write Cycle Time WC t Chip Enable CW Time to End of Write t Address Valid to AW End of Write t Address Set-up Time AS t Write Pulse Width WP t Address Hold Time AH t Data Valid to End DW of Write ...
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... Figure 1. Output Load * including scope and test fixture. Note: Because of the ultra-high speed of the P4C163/L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the V planes directly up to the contactor fingers. A 0.01 µ ...
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... P4C163/163L ORDERING INFORMATION SELECTION GUIDE The P4C163/L is available in the following temperature, speed and package options. The P4C163L is only available over the military temperature range. Temperature Package Range Commercial Plastic DIP Plastic SOJ Miliitary Side Brazed DIP Temperature LCC CERPACK Military Side Brazed DIP ...
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... BSC L 0.125 0.200 Q 0.015 0.070 S1 0.005 - S2 0.005 - CERPACK CERAMIC FLAT PACKAGE Pkg # F4 # Pins 28 Symbol Min Max A 0.060 0.090 b 0.015 0.022 c 0.004 0.009 D - 0.730 E 0.330 0.380 e 0.050 BSC k 0.005 0.018 L 0.250 0.370 Q 0.026 0.045 S - 0.085 S1 0.005 - Document # SRAM120 REV C P4C163/163L Page ...
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... P4C163/163L SOJ SMALL OUTLINE IC PACKAGE J5 Pkg # # Pins 28 (300 mil) Symbol Min Max A 0.120 0.148 A1 0.078 - b 0.014 0.020 C 0.007 0.011 D 0.700 0.730 e 0.050 BSC E 0.335 BSC E1 0.292 0.300 E2 0.267 BSC Q 0.025 - RECTANGULAR LEADLESS CHIP CARRIER Pkg # L5 # Pins 28 Symbol Min Max A 0.060 0.075 A1 0 ...
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... PLASTIC DUAL IN-LINE PACKAGE P5 Pkg # # Pins 28 (300 mil) Symbol Min Max A - 0.210 0.014 0.023 b2 0.045 0.070 C 0.008 0.014 D 1.345 1.400 E1 0.270 0.300 E 0.300 0.380 e 0.100 BSC eB - 0.430 L 0.115 0.150 0° 15° Document # SRAM120 REV C P4C163/163L Page ...
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... P4C163/163L REVISIONS DOCUMENT NUMBER: SRAM120 DOCUMENT TITLE: P4C164 / P4C163L ULTRA HIGH SPEED STATIC CMOS RAMS ORIG. OF ISSUE REV. DATE CHANGE OR 1997 DAB A Oct-05 JDB B Jul-06 JDB C Aug-06 JDB Document # SRAM120 REV C DESCRIPTION OF CHANGE New Data Sheet Change logo to Pyramid Added Lead-Free Designation ...