P4C1048L PYRAMID [Pyramid Semiconductor Corporation], P4C1048L Datasheet
P4C1048L
Related parts for P4C1048L
P4C1048L Summary of contents
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... The input/output pins stay in the HIGH Z state when either CE is HIGH LOW. The P4C1048L is packaged in a 32-pin 445 mil plastic SOP, 32-pin TSOP II, or 600 mil plastic or ceramic side- brazed DIP. PIN CONFIGURATION ...
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... P4C1048L RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE Temperature Range (Ambient) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Military (-55°C to 125°C) MAXIMUM RATINGS (a) Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet ...
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... Max GND to V OUT Max Max., Outputs Open Max Outputs Open P4C1048L P4C1048L Unit Min Max V +0.5 2 0.8 (c) –0 –0 –0.5 (c) 0.2 V 0.4 V 2.4 V –10 +10 µA Mil. ...
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... P4C1048L AC ELECTRICAL CHARACTERISTICS - READ CYCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol Parameter t Read Cycle Time RC t Address Access Time AA Chip Enable Access t AC Time Output Hold from t OH Address Change Chip Enable Output in Low Z Chip Disable Output in High Z ...
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... Document # SRAM129 REV D 4. Transition is measured ± 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 5. READ Cycle Time is measured from the last valid address to the first transitioning address. P4C1048L Page ...
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... P4C1048L AC CHARACTERISTICS - WRITE CYCLE (Over Recommended Operating Temperature & Supply Voltage) Symbol Parameter t Write Cycle Time WC Chip Enable Time End of Write Address Valid End of Write Address Set- Time t Write Pulse Width WP Address Hold t AH Time Data Valid to End ...
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... Figure 1. Output Load * including scope and test fixture. Note: Because of the high speed of the P4C1048L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the V directly up to the contactor fingers. A 0.01 µ ...
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... P4C1048L DATA RETENTION Symbol Parameter V V for Data Retention Data Retention Current CCDR Chip Deselect to Data t Retention Time CDR t Operating Recovery Time -0.2V -0. LOW V DATA RETENTION WAVEFORM CC Document # SRAM129 REV D Test Conditions CE V -0.2V -0. ...
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... ORDERING INFORMATION SELECTION GUIDE The P4C1048L is available in the following temperature, speed and package options. Temperature Package Range Commercial Plastic DIP (600 mil) Side Brazed DIP (600 mil) Plastic SOP (445 mil) TSOP II Industrial Plastic DIP (600 mil) Side Brazed DIP (600 mil) ...
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... P4C1048L SIDEBRAZED DUAL IN-LINE PACKAGE Pkg # C10 # Pins 32 (600 mil) Symbol Min Max A - 0.225 b 0.014 0.026 b2 0.045 0.065 C 0.008 0.018 D - 1.680 E 0.510 0.620 eA 0.600 BSC e 0.100 BSC L 0.125 0.200 Q 0.015 0.070 S1 0.005 - S2 0.005 - SOIC/SOP SMALL OUTLINE IC PACKAGES Pkg # S12 # Pins 32 (445 Mil) ...
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... E1 0.526 0.548 E 0.590 0.610 e 0.100 BSC eB 0.600 BSC L 0.120 0.150 0° 15° TSOP II PACKAGE Pkg # T4 # Pins 32 Symbol Min Max A 0.037 0.041 A - 0.047 2 b 0.012 0.020 D 0.395 0.405 E 0.820 0.831 e 0.050 BSC H 0.455 0.471 D Document # SRAM129 REV D P4C1048L Page ...
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... P4C1048L REVISIONS DOCUMENT NUMBER: SRAM129 DOCUMENT TITLE: P4C1048L LOW POWER 512K x 8 CMOS STATIC RAM ORIG. OF ISSUE REV. DATE CHANGE OR Oct-05 JDB A Nov-06 JDB B Dec-06 JDB C May-07 JDB Jul-07 JDB D Document # SRAM129 REV D DESCRIPTION OF CHANGE New Data Sheet Minor corrections to DC Electrical Characteristics and Data Retention tables Update SOIC/SOP package drawing ...