P4C149-35PC Pyramid Semiconductor Corporation, P4C149-35PC Datasheet
P4C149-35PC
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P4C149-35PC Summary of contents
Page 1
... The P4C148 enters the standby mode when the chip enable (CE) goes HIGH; with CMOS input levels, power consumption is extremely low in this mode. The P4C149 features a fast chip select capability using CS. The CMOS memories require no clocks or refreshing, and have equal access and cycle times. Inputs are fully TTL-compatible. The RAMs operate from a single 5V ± ...
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... Value Temperature Under – +125 Bias Storage Temperature – +150 Power Dissipation 1.0 DC Output Current 50 (4) = 25° 1.0MHz) A Parameter Conditions Typ. Unit Input Capacitance Output Capacitance OUT P4C148 P4C149 Min. Min. Max. Max. 2.4 2.4 0.4 0.4 2.2 2.2 V +0 –0.5 0.8 –0.5 0.8 (3) (3) – ...
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... Chip Enable Access Time (P4C148 Chip Enable Access Time (P4C149 Output Hold from Address Change OH t Chip Enable to Output in Low Z (P4C149 Chip Disable to Output in High Z (P4C149 Read Command Setup Time RCS t Read Command Hold Time RCH t Chip Enable to Power Up Time (P4C148 ...
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... P4C148/P4C149 AC CHARACTERISTICS—WRITE CYCLE ( ± 10%, All Temperature Ranges) CC Sym Parameter t Write Cycle Time WC t Chip Enable Time to End of Write CW t Address Valid to End of Write AW t Address Set-up Time AS t Write Pulse Width WP t Address Hold Time from End of Write AH t Data Valid to End of Write ...
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... V reflections, proper termination must be used; for example environment should be terminated into a 50 load with 1.73V (Thevenin and ground Voltage) at the comparator input, and a 116 resistor must be used in CC series with D OUT P4C148/P4C149 Output ...
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... P4C148/P4C149 ORDERING INFORMATION SELECTION GUIDE The P4C148/P4C149 are available in the following temperature, speed and package options. Temperature Package Range Plastic DIP -10PC Commercial Temperature Side Brazed DIP -10CC CERDIP Side Brazed DIP Military Temperature LCC (290 x 430 mil) LCC (295 x 335 mil) ...
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... S1 0.005 - S2 0.005 - CERDIP DUAL IN-LINE PACKAGES D1 Pkg # # Pins 18 (300 Mil) Symbol Min Max A - 0.200 b 0.014 0.026 b2 0.045 0.065 C 0.008 0.018 D - 0.960 E 0.220 0.310 eA 0.300 BSC e 0.100 BSC L 0.125 0.200 Q 0.015 0.070 S1 0.005 - 0° 15° Document # SRAM104 REV B P4C148/P4C149 Page ...
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... P4C148/P4C149 RECTANGULAR LEADLESS CHIP CARRIER L7 Pkg # # Pins 18 Symbol Min Max A 0.060 0.075 A1 0.050 0.065 B1 0.022 0.028 D 0.280 0.305 D1 .150 BSC D2 .075 BSC D3 - 0.305 E 0.417 0.440 E1 0.200 BSC E2 0.100 BSC E3 - 0.440 e 0.050 BSC h 0.040 REF j 0.020 REF L 0.045 0.055 L1 0.075 0.090 L2 0.075 ...
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... PLASTIC DUAL IN-LINE PACKAGE P1 Pkg # # Pins 18 (300 Mil) Symbol Min Max A - 0.210 A1 0.015 - b 0.014 0.022 b2 0.045 0.070 C 0.008 0.014 D 0.880 0.920 E1 0.240 0.280 E 0.300 0.325 e 0.100 BSC eB - 0.430 L 0.115 0.150 0° 15° Document # SRAM104 REV B P4C148/P4C149 Page ...
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... P4C148/P4C149 REVISIONS DOCUMENT NUMBER: SRAM104 DOCUMENT TITLE: P4C148/P4C149 ULTRA HIGH SPEED STATIC CMOS RAMS ORIG. OF ISSUE REV. DATE CHANGE OR 1997 DAB A Oct-05 JDB B Apr-07 JDB Document # SRAM104 REV B DESCRIPTION OF CHANGE New Data Sheet Change logo to Pyramid Added 45 and 55 ns speeds ...