com90c66 Standard Microsystems Corp., com90c66 Datasheet - Page 67

• Manufacturer Part Number: com90c66
• Description: Arcnet Controller/transceiver With At Interface And On-chip Ram Corporation
• Manufacturer: Standard Microsystems Corp.

PAGE
37,40
26
48
15
3
3
4
Description of Pin Functions, Pin 53
Configuration Register, Bit 2
Wait State Details section;
Table 13 - IOCHRDY and n0WS
Signal Behavior
Figure 14 - Zero Wait State and
IOCHRDY Timing
Description of Pin Functions - Pin 74
Description of Pin Functions - Pins
66, 67
Figures 4, 5 - Memory Selector,
PROM Selector
SECTION/FIGURE/ENTRY
67
In Revision D, The nENROM signal does not
affect the timing of IOCHRDY.
For Revision D, the second sentence in the
Description should read "A logic '1' on this bit
negates the IOCHRDY signal for at least two
XTAL1 clocks, creating one wait state".
For Revision D, the fourth paragraph under Wait
State Details should convey that the IOCHRDY
signal, when used, is always negated for at least
two XTAL1 clocks.
distinction made between RAM, internal register,
PROM, and external register cycles. All cycles
will negate IOCHRDY for at least two XTAL1
clocks if IOCHRDY is used. The entry in Table
13 which correlates to the IOCHRDY signal
when the Wait State Bit=1 should read "Negated
for Two to Three XTAL1 Clocks".
For Revision D, the timing parameter for t5
should be a minimum of 100 nsec, and a
maximum of 165 nsec.
For Revision D, the BALE signal is no longer
required to latch the unlatched addresses. All
addresses are latched by the leading edge of the
nMEMR and nMEMW signals for Revision D.
BALE must be tied high or left disconnected if
the device is placed in 8-bit mode.
For Revision D, the leading edge of these
signals automatically latch addresses.
device is in 8-bit mode, the BALE signal should
be tied high or left disconnected, and the
nMEMR
responsible for latching the unlatched addresses.
For Revision D, Figures 4 and 5 should contain
a second Transparent Latch, controlled by the
Control Signal.
disconnected, the address is latched by only the
second latch-stage, which is controlled only by
the nMEMR and nMEMW signals. If BALE is
connected to the bus, the address is latched by
both the first and second stage latches.
and
nMEMW
CORRECTION
If BALE is tied high or left
There should be no
signals
should
If the
be