com90c66 Standard Microsystems Corp., com90c66 Datasheet - Page 4

• Manufacturer Part Number: com90c66
• Description: Arcnet Controller/transceiver With At Interface And On-chip Ram Corporation
• Manufacturer: Standard Microsystems Corp.

75-84, 2-
PIN NO.
13-20,
PLCC
63, 62
22-29
11
71
12
74
64
65
Address 0-19
Data 0-15
nTransceiver
Direction
Control
I/O Channel
Ready
Address
Enable
Address Latch
Enable
nI/O Read
nI/O Write
NAME
A0-A19
D0-D15
nTOPL,
nTOPH
IOCHRDY
AEN
BALE
nIOR
nIOW
DESCRIPTION OF PIN FUNCTIONS
SYMBOL
PROCESSOR INTERFACE
Input. These signals are connected to the address lines
of the host processor and are used to access memory
and I/O locations of the COM90C66, as well as to access
the external ROM through the COM90C66.
Input/Output.
transmit data to and from the internal registers and buffer
memory of the COM90C66 and are connected to weak
internal pull-up resistors.
Output. These active low signals control the data bus
transceiver. When these signals are high, data gets sent
from the PC to the COM90C66. When these signals are
low, data gets sent from the COM90C66 to the PC, or
from the PROM to the PC if the PROM signal is also low.
Output. This signal, when low, is optionally used by the
COM90C66 to extend host cycles. This is an open-drain
signal. An external pull-up resistor is typically provided
by the system.
Input. This signal, when low, acts as a qualifier for I/O
Address Selection.
decoding is disabled. This signal has no effect on
Memory Address Selection.
Input.
COM90C66 to latch the A0-A19 lines and the nSBHE
signal via an internal transparent latch. This signal is
connected to a weak internal pull-up resistor.
Input.
microprocessor to indicate an I/O Read operation. A low
level on this pin when the COM90C66 is accessed
enables
COM90C66.
Input.
microprocessor to indicate an I/O Write operation. A low
pulse on this pin when the COM90C66 is accessed
enables data from the Data Bus into the internal registers
of the COM90C66.
4
The falling edge of this signal is used by the
This active low signal is issued by the host
This active low signal is issued by the host
data
These signals are used by the host to
from
DESCRIPTION
When the signal is high, I/O
the
internal
registers
of
the