com90c66 Standard Microsystems Corp., com90c66 Datasheet - Page 23

• Manufacturer Part Number: com90c66
• Description: Arcnet Controller/transceiver With At Interface And On-chip Ram Corporation
• Manufacturer: Standard Microsystems Corp.

BIT
7
6
5
4
3
2
1
0
Receiver Inhibited
(not used)
(not used)
Power On Reset
Test
Reconfiguration
Transmitter
Message
Acknowledged
Transmitter
Available
BIT NAME
SYMBOL
RI
POR
TEST
RECON
TMA
TA
Table 5 - Status Register
This bit, if high, indicates that a packet has been deposited
into the RAM buffer page nn as specified by the last ENABLE
RECEIVE TO PAGE nn command.
received until this command is issued, and once the message
has been received, the RI bit gets set, thereby inhibiting the
receiver.
RECEIVE TO PAGE nn command. This bit, when set, will
cause an interrupt if the corresponding bit of the Interrupt
Mask Register is also set.
This bit is undefined.
This bit is undefined.
This bit, if high, indicates that the COM90C66 has been reset
by either a software reset, a hardware reset, or setting the
Node ID = 00H.
FLAGS command.
This bit is intended for test and diagnostic purposes. It is a
logic "0" under normal operating conditions.
This bit, if high, indicates that the Line Idle Timer has timed
out because the RXIN pin (pin 57) was idle for 82
RECON bit is cleared during a CLEAR FLAGS command.
This bit, when set, will cause an interrupt if the corresponding
bit in the Interrupt Mask Register is also set. The interrupt
service routine should consist of looking at the MYRECON bit
of the Diagnostic Status Register to make sure that there are
not consecutive reconfigurations caused by this node.
This bit, if high, indicates that the packet transmitted as a
result of an ENABLE TRANSMIT FROM PAGE nn command
has been positively acknowledged. This bit should only be
considered valid after the TA bit (bit 0) is set. Broadcast
messages are never acknowledged. The TMA bit is cleared
by issuing the ENABLE TRANSMIT FROM PAGE nn
command.
This bit, if high, indicates that the transmitter is available for
transmitting. This bit is set at the conclusion of an ENABLE
TRANSMIT FROM PAGE nn command or upon execution of
a DISABLE TRANSMITTER command. The TA bit is cleared
by issuing the ENABLE TRANSMIT FROM PAGE nn
command after the node next receives the token. This bit,
when set, will cause an interrupt if the corresponding bit in
the Interrupt Mask Register is also set.
23
The RI bit is cleared by issuing an ENABLE
The POR bit is cleared by the CLEAR
DESCRIPTION
No messages will be
S. The