com90c66 Standard Microsystems Corp., com90c66 Datasheet - Page 66

• Manufacturer Part Number: com90c66
• Description: Arcnet Controller/transceiver With At Interface And On-chip Ram Corporation
• Manufacturer: Standard Microsystems Corp.

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8-Bit vs. 16-Bit Accesses
Figure 12 - nMEMCS16 Generation
Figure 15 - Read RAM Cycle -t7, t11;
Figure 16 - Write RAM Cycle - t6, t9
Figure 12A - nIOCS16 Generation
Figure 17 - Read I/O Cycle - t6;
Figure 18 - Write I/O Cycle - t5
SECTION/FIGURE/ENTRY
66
The following paragraph should be inserted after
the heading 8-Bit Vs. 16-Bit Accesses : "The
COM90C66 defaults to the appropriate bus-
width mode when Pin 60 is connected to a signal
which is low only in the presence of a 16-bit bus,
such as connector D18 of the AT bus (AT
ground). If Pin 60 senses a low level, the device
defaults to 16-bit mode. If Pin 60 senses a high
level (such as when Pin 60 is left disconnected),
the device defaults to 8-bit mode. In either case,
bit 7 of the Configuration Register automatically
reflects the bus-width default.
override the default obtained via Pin 60 by
writing a new value into bit 7 of the Configuration
Register."
For Revision D, the transparent latch and the
BALE signal should not appear in Figure 12.
The addresses are actually latched by the device
for proper addressing, but the nMEMCS16 signal
is generated by the addresses which come
directly into the device rather than the internally
latched version of these addresses.
For Revision D, parameters t7 of Figure 15 and
t6 of Figure 16 should not reference BALE, but
should instead read "A19-A11 to nMEMCS16
Low (Latched) (2K RAM Decode)".
parameters t11 of Figure 15 and t9 of Figure 16
should apply to both Latched and Unlatched
versions of the nMEMCS16 signal.
For Revision D, the transparent latch and the
BALE signal should not appear in Figure 12A.
The addresses are actually latched by the device
for proper addressing, but the nIOCS16 signal is
generated by the addresses which come directly
into the device rather than the internally latched
version of these addresses.
For Revision D, t6 of Figure 17 and t5 of Figure
18 should not reference BALE, but should
instead read "A2-A15, AEN Low to nIOCS16
Low" Also, parameters should be added for the
deactivation of nIOCS16.
CORRECTION
The user may
Also,