com90c66 Standard Microsystems Corp., com90c66 Datasheet - Page 53
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com90c66
Manufacturer Part Number
com90c66
Description
Arcnet Controller/transceiver With At Interface And On-chip Ram Corporation
Manufacturer
Standard Microsystems Corp.
Datasheet
1.COM90C66.pdf
(76 pages)
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AEN
* For latched address, t1 and t2 do not apply. Please refer to Figure 21 for Latched Addresss
** 200 nS minimum inactive time on consecutive writes to the Data Register of the COM90C66.
A0-A15,
nSBHE
BALE
nIOW
D0-D7 or
D0-D15
nTOPL
nIOCS16
nTOPH
Mode.
t1
t2
t3
t4
t5
t6
t7
t8
Address, nSBHE Set Up to BALE Low *
Address, nSBHE Hold after BALE Low *
Address, nSBHE, AEN Set Up to nIOW Low
Valid Data Set Up to nIOW High
Data Hold Time from nIOW High
nIOW High to BALE High (Next Address)
AEN Hold after nIOW High
A2-A15, AEN Low, BALE High to nIOCS16 Low
t5
t1
Parameter
t3
FIGURE 18 - WRITE I/O CYCLE
VALID
t2
53
min
20
30
10
20
25
30
0
9
VALID DATA
t4
typ
t6
t8
t7
max
25
**
units
nS
nS
nS
nS
nS
nS
nS
nS