com90c66 Standard Microsystems Corp., com90c66 Datasheet - Page 22

• Manufacturer Part Number: com90c66
• Description: Arcnet Controller/transceiver With At Interface And On-chip Ram Corporation
• Manufacturer: Standard Microsystems Corp.

process works.
decoded through a 3 to 12 Decoder to generate
a 12-bit value. These 12 bits are compared to
the A15-A4 lines of the address bus in order to
determine which block of 16 I/O locations will be
used by the chip. A logic "0" on the AEN signal
enables the I/O decoding process. Tables 3 and
4 illustrate the COM90C66 register map.
Reserved locations should not be accessed.
INTERNAL REGISTERS
The COM90C66 contains internal registers
which may be accessed by the microprocessor.
must be written as logic "0".
Status Register
The COM90C66 Status Register is an 8-bit
read-only register which can be accessed by the
microprocessor. All of the bits in this register
(except for bits 5 and 6) are software-compatible
with previous SMSC ARCNET devices.
Extended
Configuration Register.
contents are traditionally defined as in Table 5.
The Status Register contents are defined
differently
operation.
Chaining" section of this document for these
definitions. The Status Register defaults to the
value 1XX1 0001 upon either hardware or
software reset.
Interrupt Mask Register (IMR)
The COM90C66 is capable of generating an
interrupt signal when certain status bits become
true. A write to the IMR specifies which status
bits will be enabled to generate the interrupt.
The bit positions in the IMR are in the same
position as their corresponding status bits in the
Status Register, and a logic "1" in a particular
position enables the corresponding interrupt.
While the Receiver Inhibited, Reconfiguration,
All undefined bits are read as undefined and
Timeout
during
Please refer to the "Command
The IOS2-IOS0 pins are
the
bits
Command
The Status Register
are
now
Chaining
in
The
the
22
and Transmitter Available status bits are
capable of generating an interrupt if enabled, the
TMA status bit will never cause an interrupt.
The IMR takes on the following bit definition:
The three maskable status bits are ANDed with
their respective mask bits, and the results are
ORed to produce the processor interrupt signal
INTR. An RI or TA interrupt is masked when the
corresponding mask bit is reset to logic "0", but
will reappear when the corresponding mask bit
is set to logic "1" again, unless the interrupt
status condition has been cleared by this time.
A RECON interrupt is cleared when the CLEAR
FLAGS command is issued. The Interrupt Mask
Register defaults to the value 0000 0000 upon
either hardware or software reset.
Diagnostic Status Register
The Diagnostic Status Register contains three
read-only bits which give the user the ability to
troubleshoot network or node operation.
various combinations of these bits and the
Transmitter Off bit of the Configuration Register
represent different situations and can be used
during troubleshooting. These bits are reset to
logic "0" upon reading the Diagnostic Status
Register or upon software or hardware reset.
The register contents are as in Table 6. The
Diagnostic Status Register defaults to the value
0X00 XXXX upon either hardware or software
reset.
Command Register
Execution
performing a processor I/O write with the written
data defining the commands listed in Table 7.
Any combinations of written data other than
those listed in Table 7 are not permitted and
may result in incorrect chip and/or network
operation.
BIT
RI
7
BIT
X
6
of
BIT
5
X
commands
BIT
X
4
BIT
X
3
are
BIT 2
CON
RE-
initiated
BIT
X
1
The
BIT
TA
0
by