s3c72m9 Samsung Semiconductor, Inc., s3c72m9 Datasheet - Page 174
s3c72m9
Manufacturer Part Number
s3c72m9
Description
The S3c72m5/s3c72m7/s3c72m9 Single-chip Cmos Microcontroller Has Been Designed For High Performance Using Samsung S
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.S3C72M9.pdf
(382 pages)
- Current page: 174 of 382
- Download datasheet (2Mb)
SAM47 INSTRUCTION SET
LDI —
LDI
Operation:
Description:
Example:
5-70
Load Data Memory and Increment
Assume that register pair HL contains the address 2FH and internal RAM location 2FH contains the
value 0FH:
LD
LDI
JPS
JPS
The instruction 'JPS XXX' is skipped since an overflow occurred after the 'LDI A,@HL' and the
instruction 'JPS YYY' is executed.
dst,src
The contents of a data memory location are loaded into the accumulator, and the contents of the
register L are incremented by one. If an overflow occurs (e.g., if the resulting value in register L is
0H), the next instruction is skipped. The contents of data memory and the carry flag value are not
affected.
Operand
Operand
A,@HL
A,@HL
HL,#2FH
A,@HL
XXX
YYY
Load indirect data memory to A; increment register L
contents and skip on overflow
1
0
0
Binary Code
Operation Summary
0
; A
; Skip
; H
1
0
2H and L
(HL) and L
S3C72M5/C72M7/C72M9/P72M9 (Preliminary Spec)
1
0
0H
A
skip if L = 0H
L+1
(HL), then L
Operation Notation
Bytes
1
L+1;
Cycles
2 + S
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