SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 86

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

www.national.com
General Configuration Block
2:1
Bit
16
15
14
13
12
11
10
9
8
7
6
5
4
3
Table 3-2. Multiplexing, Interrupt Selection, and Base Address Registers (Continued)
Description
Delay HSYNC. HSYNC delay by two TFT clock cycles.
0: There is no delay on HSYNC.
1: HYSNC is delayed twice by rising edge of TFT clock. Enables delay between VSYNC and HSYNC suited for TFT dis-
Reserved. Write as read.
IBUS16 (Invert BUS16). This bit inverts the meaning of MCR[3] (bit 3 of this register).
0: BUS16 is as described for MCR[3].
1: BUS16 meaning is inverted: if MCR[3] = 0, ROMCS# access is 16 bits wide; if MCR[3] = 1, ROMCS# access is 8 bits
Reserved. Must be set to 0.
IO1ZWS (Enable ZWS# for IOCS1# Access). This bit enables internal activation of ZWS# (Zero Wait States) control for
IOCS1# access.
0: ZWS# is not active for IOCS1# access.
1: ZWS# is active for IOCS1# access.
IO0ZWS (Enable ZWS# for IOCS0# Access). This bit enables internal activation of ZWS# (Zero Wait States) control for
IOCS0# access.
0: ZWS# is not active for IOCS0# access.
1: ZWS# is active for IOCS0# access.
DOCZWS (Enable ZWS# for DOCCS# Access). This bit enables internal activation of ZWS# (Zero Wait States) control for
DOCCS# access.
0: ZWS# is not active for DOCCS# access.
1: ZWS# is active for DOCCS# access.
ROMZWS (Enable ZWS# for ROMCS# Access). This bit enables internal activation of ZWS# (Zero Wait States) control for
ROMCS# access.
0: ZWS# is not active for ROMCS# access.
1: ZWS# is active for ROMCS# access.
IO1_16 (Enable 16-Bit Wide IOCS1# Access). This bit enables the16-line access to IOCS1# in the Sub-ISA interface.
0: 8-bit wide IOCS1# access is used.
1: 16-bit wide IOCS1# access is used.
IO0_16 (Enable 16-Bit Wide IOCS0# Access). This bit enables the 16-line access to IOCS0# in the Sub-ISA interface.
0: 8-bit wide IOCS0# access is used.
1: 16-bit wide IOCS0# access is used.
DOC16 (Enable 16-Bit Wide DOCCS# Access). This bit enables the 16-line access to DOCCS# in the Sub-ISA interface.
0: 8-bit wide DOCCS# access is used.
1: 16-bit wide DOCCS# access is used.
Reserved. Write as read.
IRTXEN (Infrared Transmitter Enable). This bit enables drive of Infrared transmitter output.
0: IRTX+SOUT3 line (EBGA ball J3 / TEPBGA ball C11) is HiZ.
1: IRTX+SOUT3 line (EBGA ball J3 / TEPBGA ball C11) is enabled.
BUS16 (16-Bit Wide Boot Memory). (Read Only) This bit reports the status of the BOOT16 strap (EBGA ball G4 / TEP-
BGA ball C8). If the BOOT16 strap is pulled high, at reset 16-bit access to ROM in the Sub-ISA interface is enabled.
MCR[14] = 1 inverts the meaning of this register.
0: 8-bit wide ROM.
1: 16-bit wide ROM.
Reserved. Write as read.
play.
wide.
(Continued)
86
Revision 3.0