SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 131

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

Revision 3.0
SuperI/O Module
4.7.3
The ACK cycle consists of two signals: the ACK clock pulse
sent by the master with each byte transferred, and the ACK
signal sent by the receiving device (see Figure 4-15).
The master generates the ACK clock pulse on the ninth
clock pulse of the byte transfer. The transmitter releases
Acknowledge (ACK) Cycle
by Transmitter
Data Output
Data Output
by Receiver
ABD
ABC
ABC
(Continued)
Start
Condition
S
Start
Condition
S
Figure 4-16. ACCESS.bus Acknowledge Cycle
MSB
Figure 4-15. ACCESS.bus Data Transaction
1
2 3 - 6
1
Byte Complete
Interrupt Within
Receiver
2 3 - 6
7
8
7
ACK
131
9
8
the ABD line (permits it to go high) to allow the receiver to
send the ACK signal. The receiver must pull down the ABD
line during the ACK clock pulse, signalling that it has cor-
rectly received the last data byte and is ready to receive the
next byte. Figure 4-16 illustrates the ACK cycle.
Acknowledge
Signal From Receiver
9
1
While Interrupt
Clock Line Held
Low by Receiver
is Serviced
2
3 - 8
Acknowledge
Signal From Receiver
Transmitter Stays Off Bus
During Acknowledge Clock
ACK
9
Stop
Condition
P
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