SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 194

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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Core Logic Module
00h-01h
02h-03h
04h-05h
06h-07h
08h
09h-0Bh
0Ch
0Dh
0Eh
0Fh
10h-13h
14h-17h
18h-1Bh
1Ch-1Fh
20h-23h
24h-27h
28h-2Bh
2Ch-2Dh
2Eh-2Fh
30h-3Fh
40h-43h
44h-47h
48h-4Bh
4Ch-4Fh
50h-53h
54h-57h
58h
59h-FFh
60h-63h
64h-67h
68h-FFh
00h-03h
04h-07h
08h-0Bh
F5BAR0+
I/O Offset
F5 Index
Width
Width
(Bits)
(Bits)
Table 5-24. F5: PCI Header Registers for X-Bus Expansion Support Summary
32
16
16
16
16
24
32
32
32
32
32
---
16
16
---
32
32
32
32
32
32
---
32
32
---
32
32
32
8
8
8
8
8
8
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 5-25. F5BAR0: I/O Control Support Registers Summary
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
---
---
---
---
(Continued)
Name
Vendor Identification Register
Device Identification Register
PCI Command Register
PCI Status Register
Device Revision ID Register
PCI Class Code Register
PCI Cache Line Size Register
PCI Latency Timer Register
PCI Header Type Register
PCI BIST Register
Base Address Register 0 (F5BAR0) — Sets the base address for
the X-Bus Expansion support registers (summarized in
Table 5-25.)
Base Address Register 1 (F5BAR1) — Reserved for possible
future use by the Core Logic module.
Base Address Register 2 (F5BAR2) — Reserved for possible
future use by the Core Logic module.
Base Address Register 3 (F5BAR3) — Reserved for possible
future use by the Core Logic module.
Base Address Register 4 (F5BAR4) — Reserved for possible
future use by the Core Logic module.
Base Address Register 5 (F5BAR5) — Reserved for possible
future use by the Core Logic module.
Reserved
Subsystem Vendor ID
Subsystem ID
Reserved
F5BAR0 Base Address Register Mask
F5BAR1 Base Address Register Mask
F5BAR2 Base Address Register Mask
F5BAR3 Base Address Register Mask
F5BAR4 Base Address Register Mask
F5BAR5 Base Address Register Mask
F5BARx Initialized Register
Reserved
Scratchpad for Chip Number
Scratchpad for Configuration Block Address
Reserved
Name
I/O Control Register 1
I/O Control Register 2
I/O Control Register 3
194
FFFFFFC1h
010C0007h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
00000002h
00009000h
068000h
100Bh
0505h
0000h
0280h
100Bh
0505h
Reset
Value
Reset
Value
00h
00h
00h
00h
00h
00h
00h
00h
xxh
---
(Table 5-39)
(Table 5-40)
Reference
Reference
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