SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 208

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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Core Logic Module
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Index 5Ch
Indicates target interrupts for signals INTB# and INTA#.
Note:
Index 5Dh
Indicates target interrupts for signals INTD# and INTC#. Note that INTD# is muxed with IDE_DATA7 (selection made via PMR[24]) and
INTC# is muxed with GPIO19+IOCHRDY (selection made via PMR[9,4]). See Table 3-2 on page 81 for PMR bit descriptions.
Note:
Index 5Eh-5Fh
Index 60h-63h
31:8
7:4
3:0
7:4
3:0
Bit
7
6
5
4
3
2
The target interrupt must first be configured as level sensitive via I/O Ports 4D0h and 4D1h in order to maintain PCI interrupt
compatibility.
The target interrupt must first be configured as level sensitive via I/O Ports 4D0h and 4D1h in order to maintain PCI interrupt
compatibility.
Description
INTB# (EBGA Ball AF1 / TEPBGA Ball C26) Target Interrupt.
0000: Disable
0001: IRQ1
0010: Reserved
0011: IRQ3
INTA# (EBGA Ball AE3 / TEPBGA Ball D26) Target Interrupt.
0000: Disable
0001: IRQ1
0010: Reserved
0011: IRQ3
INTD# (EBGA Ball B22 / TEPBGA Ball AA2) Target Interrupt.
0000: Disable
0001: IRQ1
0010: Reserved
0011: IRQ3
INTC# (EBGA Ball H4 / TEPBGA Ball C9) Target Interrupt.
0000: Disable
0001: IRQ1
0010: Reserved
0011: IRQ3
Reserved. Must be set to 0.
SUSP_3V Shut Down PLL5. Allow internal SUSP_3V to shut down PLL5.
0: Clock generator is stopped when internal SUSP_3V is active.
1:
SUSP_3V Shut Down PLL4. Allow internal SUSP_3V to shut down PLL4
0: Clock generator is stopped when internal SUSP_3V is active.
1:
SUSP_3V Shut Down PLL3. Allow internal SUSP_3V to shut down PLL3.
0: Clock generator is stopped when internal SUSP_3V is active.
1:
SUSP_3V Shut Down PLL2. Allow internal SUSP_3V to shut down PLL2.
0: Clock generator is stopped when internal SUSP_3V is active.
1:
SUSP_3V Shut Down PLL6. Allow internal SUSP_3V to shut down PLL6.
0: Clock generator is stopped when internal SUSP_3V is active.
1:
ACPI C3 SUSP_3V Enable. Allow internal SUSP_3V to be active during C3 state.
0: Disable.
1: Enable.
Clock generator continues working when internal SUSP_3V is active.
Clock generator continues working when internal SUSP_3V is active.
Clock generator continues working when internal SUSP_3V is active..
Clock generator continues working when internal SUSP_3V is active.
Clock generator continues working when internal SUSP_3V is active.
(Continued)
0100: IRQ4
0101: IRQ5
0110: IRQ6
0111: IRQ7
0100: IRQ4
0101: IRQ5
0110: IRQ6
0111: IRQ7
0100: IRQ4
0101: IRQ5
0110: IRQ6
0111: IRQ7
0100: IRQ4
0101: IRQ5
0110: IRQ6
0111: IRQ7
PCI Interrupt Steering Register 1 (R/W)
PCI Interrupt Steering Register 2 (R/W)
ACPI Control Register (R/W)
Reserved
208
1000: Reserved
1001: IRQ9
1010: IRQ10
1011: IRQ11
1000: Reserved
1001: IRQ9
1010: IRQ10
1011: IRQ11
1000: Reserved
1001: IRQ9
1010: IRQ10
1011: IRQ11
1000: Reserved
1001: IRQ9
1010: IRQ10
1011: IRQ11
1100: IRQ12
1101: Reserved
1110: IRQ14
1111: IRQ15
1100: IRQ12
1101: Reserved
1110: IRQ14
1111: IRQ15
1100: IRQ12
1101: Reserved
1110: IRQ14
1111: IRQ15
1100: IRQ12
1101: Reserved
1110: IRQ14
1111: IRQ15
Reset Value: 00000000h
Reset Value: 00h
Reset Value: 00h
Reset Value: 00h
Revision 3.0