SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 200

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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Core Logic Module
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Index 06h-07h
Index 08h
10:9
6:0
Bit
15
14
13
12
11
4
3
2
1
0
8
7
Description
Memory Write and Invalidate. Allow the Core Logic module to do memory write and invalidate cycles, if the PCI Cache
Line register (F0 Index 0Ch) is set to 32 bytes (08h).
0: Disable. (Default)
1: Enable.
Special Cycles. Allow the Core Logic module to respond to special cycles.
0: Disable.
1: Enable. (Default)
This bit must be enabled to allow the internal CPU Warm Reset signal to be triggered from a CPU Shutdown cycle.
Bus Master. Allow the Core Logic module bus mastering capabilities.
0: Disable.
1: Enable. (Default)
This bit must be set to 1.
Memory Space. Allow the Core Logic module to respond to memory cycles from the PCI bus.
0: Disable.
1: Enable. (Default)
I/O Space. Allow the Core Logic module to respond to I/O cycles from the PCI bus:
0: Disable.
1: Enable. (Default)
This bit must be set to 1 to access I/O offsets through F0BAR0 and F0BAR1 (see F0 Index 10h and 14h).
Detected Parity Error. This bit is set whenever a parity error is detected.
Write 1 to clear.
Signaled System Error. This bit is set whenever the Core Logic module asserts SERR# active.
Write 1 to clear.
Received Master Abort. This bit is set whenever a master abort cycle occurs. A master abort occurs when a PCI cycle is
not claimed, except for special cycles.
Write 1 to clear.
Received Target Abort. This bit is set whenever a target abort is received while the Core Logic module is the master for the
PCI cycle.
Write 1 to clear.
Signaled Target Abort. This bit is set whenever the Core Logic module signals a target abort. This occurs when an address
parity error occurs for an address that hits in the active address decode space of the Core Logic module.
Write 1 to clear.
DEVSEL# Timing. (Read Only) These bits are always 01, as the Core Logic module always responds to cycles for which it
is an active target with medium DEVSEL# timing.
00: Fast
01: Medium
10: Slow
11: Reserved.
Data Parity Detected. This bit is set when:
1)
2)
Write 1 to clear.
Fast Back-to-Back Capable. (Read Only) Enables the Core Logic module, as a target, to accept fast back-to-back transac-
tions.
0: Disable.
1: Enable.
This bit is always set to 1.
Reserved. (Read Only) Must be set to 0 for future use.
The Core Logic module asserts PERR# or observed PERR# asserted.
The Core Logic module is the master for the cycle in which the PERR# occurred, and PE is set (F0 Index 04h[6] = 1).
(Continued)
Device Revision ID Register (RO)
PCI Status Register (R/W)
200
Reset Value: 0280h
Reset Value: 00h
Revision 3.0