SC2200 NSC [National Semiconductor], SC2200 Datasheet - Page 226

• Manufacturer Part Number: SC2200
• Description: Thin Client On a Chip
• Manufacturer: NSC [National Semiconductor]

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Core Logic Module
Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)
Index C4h-C7h
Index C8h-CBh
Index CCh
Index CDh
31:0
31:0
6:0
6:0
Bit
7
7
Description
User Defined Device 2 Base Address. This 32-bit register supports power management (Trap and Idle timer resources) for
a PCMCIA slot or some other device in the system. The value in this register is used as the address comparator for the
device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CDh).
The Core Logic module cannot snoop addresses on the Fast-PCI bus unless it actually claims the cycle. Therefore, Traps
and Idle timers cannot support power management of devices on the Fast-PCI bus.
User Defined Device 3 Base Address. This 32-bit register supports power management (Trap and Idle timer resources) for
a PCMCIA slot or some other device in the system. The value in this register is used as the address comparator for the
device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CEh).
The Core Logic module cannot snoop addresses on the Fast-PCI bus unless the it actually claims the cycle. Therefore,
Traps and Idle timers cannot support power management of devices on the Fast-PCI bus.
Memory or I/O Mapped. Determines how User Defined Device 1 is mapped.
0: I/O.
1: Memory.
Mask.
If bit 7 = 0 (I/O):
If bit 7 = 1 (Memory):
Note:
Memory or I/O Mapped. determines how User Defined Device 2 is mapped.
0: I/O
1: Memory
Mask.
If bit 7 = 0 (I/O):
If bit 7 = 1 (Memory):
Note:
A "1" in a mask bit means that the address bit is ignored for comparison.
A "1" in a mask bit means that the address bit is ignored for comparison.
Bit 6
Bit 5
Bits [4:0] Mask for address bits A[4:0]
Bits [6:0] Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) A[8:0] are ignored.
Bit 6
Bit 5
Bits [4:0] Mask for address bits A[4:0]
Bits [6:0] Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) A[8:0] are ignored.
(Continued)
0: Disable write cycle tracking
1: Enable write cycle tracking
0: Disable read cycle tracking
1: Enable read cycle tracking
0: Disable write cycle tracking
1: Enable write cycle tracking
0: Disable read cycle tracking
1: Enable read cycle tracking
User Defined Device 2 Base Address Register (R/W)
User Defined Device 3 Base Address Register (R/W)
User Defined Device 1 Control Register (R/W)
User Defined Device 2 Control Register (R/W)
226
Reset Value: 00000000h
Reset Value: 00000000h
Reset Value: 00h
Reset Value: 00h
Revision 3.0