IDT72255LA IDT [Integrated Device Technology], IDT72255LA Datasheet - Page 3

• Manufacturer Part Number: IDT72255LA
• Description: CMOS SUPERSYNC FIFO
• Manufacturer: IDT [Integrated Device Technology]

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18
DESCRIPTION (Continued)
of the FWFT/SI input during Master Reset determines the
timing mode in use.
a single FIFO can provide, the FWFT timing mode permits
depth expansion by chaining FIFOs in series (i.e. the data
outputs of one FIFO are connected to the corresponding data
inputs of the next). No external logic is required.
Output Ready),
Flag),
grammable Almost-Full flag). The
selected in IDT Standard mode. The
selected in FWFT mode.
available for use, irrespective of timing mode.
at any point in memory. (See Table I and Table II.) Program-
mable offsets determine the flag switching threshold and can
be loaded by two methods: parallel or serial. Two default
offset settings are also provided, so that
switch at 127 or 1,023 locations from the empty boundary and
the
full boundary. These choices are made with the
Master Reset.
rising edge of WCLK, are used to load the offset registers via
the Serial Input (SI). For parallel programming,
with
offset registers via D
edge of RCLK can be used to read the offsets in parallel from
FIRST WORD FALL THROUGH/SERIAL INPUT
For applications requiring more data storage capacity than
PAE
For serial programming,
These FIFOs have five flag pins,
PAF
LD
PAE
and
threshold can be set at 127 or 1,023 locations from the
PROGRAMMABLE ALMOST-FULL (
on each rising edge of WCLK, are used to load the
(Programmable Almost-Empty flag) and
PAF
FULL FLAG/INPUT READY (
FF
can be programmed independently to switch
/
IR
n
(Full Flag or Input Ready),
.
REN
Figure 1. Block Diagram of Single 8,192 x 18 and 16,384 x 18 Synchronous FIFO
WRITE CLOCK (WCLK)
WRITE ENABLE (
SERIAL ENABLE(
HF
together with
SEN
,
PAE
together with
DATA IN (D
EF
IR
PARTIAL RESET (
EF
and
and
and
/
OR
LOAD (
PAE
(FWFT/SI)
LD
FF
OR
PAF
(Empty Flag or
on each rising
WEN
can be set to
functions are
LD
functions are
0
HF
LD
are always
- D
/ )
pin during
PAF
(Half-full
together
on each
n
)
)
)
)
)
(Pro-
72255LA
72265LA
)
IDT
Q
been selected.
The read and write pointers are set to the first location of the
FIFO. The FWFT pin selects IDT Standard mode or FWFT
mode. The
of 127 with parallel programming or a partial flag default
setting of 1,023 with serial programming. The flags are
updated according to the timing mode and default offsets
selected.
pointers to the first location of the memory. However, the
timing mode, partial flag programming method, and default or
programmed offset settings existing before Partial Reset
remain unchanged. The flags are updated according to the
timing mode and offsets in effect.
a device in mid-operation, when reprogramming partial flags
would be undesirable.
FIFO more than once. A LOW on the
RCLK edge initiates a retransmit operation by setting the read
pointer to the first location of the memory array.
operation, the chip will automatically power down. Once in the
power down state, the standby supply current consumption is
minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down
state.
speed submicron CMOS technology.
n
During Master Reset (
The Partial Reset (
The Retransmit function allows data to be reread from the
If, at any time, the FIFO is not actively performing an
The IDT72255LA/72265LA are fabricated using IDT’s high
MASTER RESET (
regardless of whether serial or parallel offset loading has
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
READ CLOCK (RCLK)
READ ENABLE (
RETRANSMIT (
EMPTY FLAG/OUTPUT READY (
PROGRAMMABLE ALMOST-EMPTY (
HALF FULL FLAG (
DATA OUT (Q
OUTPUT ENABLE (
LD
pin selects either a partial flag default setting
PRS
MRS
0
) also sets the read and write
)
- Q
) the following events occur:
)
n
)
PRS
)
)
)
RT
is useful for resetting
input during a rising
4670 drw 03
/
)
3
)