IDT72255LA IDT [Integrated Device Technology], IDT72255LA Datasheet - Page 2

• Manufacturer Part Number: IDT72255LA
• Description: CMOS SUPERSYNC FIFO
• Manufacturer: IDT [Integrated Device Technology]

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18
DESCRIPTION (Continued)
PIN CONFIGURATIONS
• The first word data latency period, from the time the first
SuperSync FIFOs are particularly appropriate for network,
video, telecommunications, data communications and other
applications that need to buffer large amounts of data.
and a Write Enable (
on every rising edge of WCLK when
output port is controlled by a Read Clock (RCLK) input and
Read Enable (
rising edge of RCLK when
(
OE
word is written to an empty FIFO to the time it can be read,
is now fixed and short. (The variable clock cycle counting
delay associated with the latency period found on previous
SuperSync devices has been eliminated on this SuperSync
family.)
The input port is controlled by a Write Clock (WCLK) input
) input is provided for three-state control of the outputs.
REN
PIN 1
) input. Data is read from the FIFO on every
WEN
GND
D17
D16
D15
D14
D13
D12
D11
D10
V
DC
D9
D8
D7
CC
) input. Data is written into the FIFO
REN
is asserted. An Output Enable
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
WEN
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
is asserted. The
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
may vary from 0 to f
are no restrictions on the frequency of one clock input with
respect to the other.
these devices: IDT Standard mode and First Word Fall Through
(FWFT) mode.
FIFO will not appear on the data output lines unless a specific
read operation is performed. A read operation, which consists
of activating
the word from internal memory to the data output lines.
clocked directly to the data output lines after three transitions
of the RCLK signal. A
accessing the first word. However, subsequent words written
to the FIFO do require a LOW on
The frequencies of both the RCLK and the WCLK signals
In IDT Standard mode, the first word written to an empty
In FWFT mode, the first word written to an empty FIFO is
There are two possible timing modes of operation with
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
REN
and enabling a rising RCLK edge, will shift
MAX
REN
with complete independence. There
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
does not have to be asserted for
4670 drw 02
REN
Q17
Q16
GND
Q15
Q14
V
Q13
Q12
Q11
GND
Q10
Q9
Q8
Q7
Q6
GND
for access. The state
CC
2