IDT72255LA IDT [Integrated Device Technology], IDT72255LA Datasheet - Page 14

• Manufacturer Part Number: IDT72255LA
• Description: CMOS SUPERSYNC FIFO
• Manufacturer: IDT [Integrated Device Technology]

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18
HIGH, inhibiting further write operations. If no reads are
performed after a reset (either
after D writes to the FIFO (D = 8,193 for the IDT72255LA and
16,385 for the IDT72265LA) See Figure 9, Write Timing
(FWFT Mode) , for the relevant timing information.
memory, but also counts the presence of a word in the output
register. Thus, in FWFT mode, the total number of writes
necessary to deassert
FF
FF
EMPTY FLAG (
Empty Flag (
EF
is HIGH, the FIFO is not empty. See Figure 8, Read Cycle,
Empty Flag and First Word Latency Timing (IDT Standard
Mode) , for the relevant timing information.
OR
empty FIFO appears valid on the outputs.
the RCLK LOW to HIGH transition that shifts the last word from
the FIFO memory to the outputs.
read (RCLK with
outputs, indicating the last word was read. Further data reads
are inhibited until
Timing (FWFT Mode) , for the relevant timing information.
RCLK.
output. In FWFT mode,
PROGRAMMABLE ALMOST-FULL FLAG (
the FIFO reaches the almost-full condition. In IDT Standard
mode, if no reads are performed after reset (
LOW after (D - m) words are written to the FIFO. The
go LOW after (8,192-m) writes for the IDT72255LA and
(16,384-m) writes for the IDT72265LA. The offset “m” is the full
offset value. The default setting for this value is stated in the
footnote of Table 1.
for the IDT72255LA and (16,385-m) writes for the IDT72265LA,
/
In IDT Standard mode,
In FWFT mode, the
The
FF
This is a dual purpose pin. In the IDT Standard mode, the
In FWFT mode, the Output Ready (
The Programmable Almost-Full flag (
in IDT Standard mode.
IR
will go LOW, inhibiting further read operations. When
EF
goes LOW at the same time that the first word written to an
/
IR
are double register-buffered outputs.
/
OR
IR
is synchronous and updated on the rising edge of WCLK.
status not only measures the contents of the FIFO
is synchronous and updated on the rising edge of
EF
) function is selected. When the FIFO is empty,
EF EF EF EF EF
REN
OR
/
OR
OR
OR
OR
OR
goes LOW again. See Figure 10, Read
= LOW). The previous data stays at the
PAF
IR
)
OR
is one greater than needed to assert
will go LOW after (8,193-m) writes
is a triple register-buffered output.
EF
MRS
is a double register-buffered
OR
goes HIGH only with a true
or
OR
PAF
PRS
) function is selected.
OR
) will go LOW when
),
MRS
stays LOW after
IR
PAF
PAF
PAF
PAF
PAF
will go HIGH
),
)
PAF
PAF
will go
will
EF
where m is the full offset value. The default setting for this
value is stated in the footnote of Table 2.
(IDT Standard and FWFT Mode) , for the relevant timing
information.
PROGRAMMABLE ALMOST-EMPTY FLAG (
when the FIFO reaches the almost-empty condition. In IDT
Standard mode, PAE will go LOW when there are n words or
less in the FIFO. The offset “n” is the empty offset value. The
default setting for this value is stated in the footnote of Table 1.
words or less in the FIFO. The default setting for this value is
stated in the footnote of Table 2.
(IDT Standard and FWFT Mode) , for the relevant timing
information.
HALF-FULL FLAG (
edge that fills the FIFO beyond half-full sets
remains LOW until the difference between the write and read
pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this
condition sets
(
FIFO, where D = 8,192 for the IDT72255LA and 16,384 for the
IDT72265LA.
or
where D = 8,193 for the IDT72255LA and 16,385 for the
IDT72265LA.
FWFT Modes) , for the relevant timing information. Because
HF
asynchronous.
DATA OUTPUTS (Q
MRS
PRS
See Figure 16, Programmable Almost-Full Flag Timing
See Figure 17, Programmable Almost-Empty Flag Timing
PAF
The Programmable Almost-Empty flag (
In FWFT mode, the
PAE
This output indicates a half-full FIFO. The rising WCLK
In IDT Standard mode, if no reads are performed after reset
In FWFT mode, if no reads are performed after reset (
See Figure 18, Half-Full Flag Timing (IDT Standard and
(Q
is updated by both RCLK and WCLK, it is considered
0
or
),
- Q
is synchronous and updated on the rising edge of WCLK.
is synchronous and updated on the rising edge of RCLK.
HF
PRS
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
17
will go LOW after (D-1/2 + 2) writes to the FIFO,
) are data outputs for 18-bit wide data.
),
HF
HF
HIGH.
will go LOW after (D/2 + 1) writes to the
HF HF HF HF HF
0
-Q
PAE
)
17
)
will go LOW when there are n+1
PAE
HF
LOW. The flag
PAE
PAE
) will go LOW
PAE
PAE
PAE
)
14
MRS