IDT72255LA IDT [Integrated Device Technology], IDT72255LA Datasheet - Page 21

• Manufacturer Part Number: IDT72255LA
• Description: CMOS SUPERSYNC FIFO
• Manufacturer: IDT [Integrated Device Technology]

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18
NOTE:
1. X = 12 for the IDT72255LA and X = 13 for the IDT72265LA.
NOTES:
1. Retransmit setup is complete after
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore,
3.
4. W
5.
WCLK
Q
WCLK
RCLK
Retransmit setup procedure. D = 8,193 for the IDT72255LA and 16,385 for the IDT72265LA.
OE
OR
0
- Q
1
SI
, W
= LOW
goes LOW at 60 ns + 2 RCLK cycles + t
n
2
, W
t
ENS
3
= first, second and third words written to the FIFO after Master Reset.
W
x
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
ENH
BIT 0
t
t
ENS
LDS
t
DS
t
ENS
t
RTS
t
RTS
OR
returns LOW.
t
t
LDH
ENH
REF
EMPTY OFFSET
.
t
t
REF
t
ENH
HF
t
SKEW2
Figure 12. Retransmit Timing (FWFT Mode)
1
2
t
PAF
1
W
x+1
BIT X
(1)
BIT 0
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
2
t
PAE
FULL OFFSET
3
t
A
t
ENH
t
REF
(5)
IR
W
1
will be LOW throughout the
(4)
BIT X
t
t
LDH
ENH
t
DH
(1)
W
4
2
t
A
4670 drw 16
4670 drw 15
t
ENH
21
W
3