IDT72255LA IDT [Integrated Device Technology], IDT72255LA Datasheet - Page 22

• Manufacturer Part Number: IDT72255LA
• Description: CMOS SUPERSYNC FIFO
• Manufacturer: IDT [Integrated Device Technology]

IDT72255LA/72265LA SUPERSYNC FIFO™
8,192 x 18, 16,384 x 18
NOTE:
1.
NOTES:
1. m =
2. D = maximum FIFO depth.
3. t
4.
Q
WCLK
RCLK
D
OE
0
0
WCLK
In IDT Standard mode: D = 8,192 for the IDT72255LA and 16,384 for the IDT72265LA.
In FWFT mode: D = 8,193 for the IDT72255LA and 16,385 for the IDT72265LA.
time between the rising edge of RCLK and the rising edge of WCLK is less than t
PAF
SKEW2
RCLK
- Q
- D
= LOW
15
PAF
15
is asserted and updated on the rising edge of WCLK only.
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
t
CLKH
offset .
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
ENS
Figure 15. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
Figure 16. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
D - (m+1) words in FIFO
t
CLKL
t
ENH
DATA IN OUTPUT
t
REGISTER
CLKH
t
CLKH
1
(2)
t
CLK
t
CLK
t
t
ENS
LDS
t
t
CLKL
DS
t
t
ENS
LDS
t
CLKL
OFFSET
PAE
2
t
PAF
t
t
t
SKEW2
ENH
DH
LDH
t
t
LDH
t
ENH
A
t
ENS
, then the
t
SKEW2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
(3)
PAF
OFFSET
PAF
PAF
deassertion time may be delayed one extra WCLK cycle.
t
ENH
D - m words in FIFO
will go HIGH (after one WCLK cycle plus t
OFFSET
PAE
t
1
t
t
DH
ENH
LDH
t
t
ENH
LDH
t
A
(2)
2
t
PAF
OFFSET
PAF
D-(m+1) words
in FIFO
4670 drw 19
4670 drw 17
4670 drw 18
PAF
( 2)
). If the
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