w65c265s Western Design Center, Inc., w65c265s Datasheet - Page 43

• Manufacturer Part Number: w65c265s
• Description: W65c265s 16?bit Microcontroller
• Manufacturer: Western Design Center, Inc.

3.5 AC Timing Diagram Notes
1.
2.
The Rise and Fall times are not programmable on the automated test system that is used for
production testing. A typical Rise and Fall time is 5-10ns; therefore, the spec indicates the duty
cycle of the clock as tested (tPWL=tCYC/2-tF).
The Rise and Fall times of indicate output Rise and Fall times. The most critical Rise and
Fall times are for PHI2 because all timing is related to PHI2.
The input Rise and Fall times can affect the input setup time (tIS), output delay time (tOD) and
hold time (tH). This must be taken into account in an application. At 2MHz and 4MHz,
the worst case input Rise and Fall times may prevent a system from working.
3.
tCYC must always be equal to or greater than four times tCYCF when FCLK is running.
Rise and Fall Times for all signals are measured on a sample basis from .3xVDD to .7xVDD.
Hold Time for all inputs and outputs is relative to the associated clock edge.
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