w65c265s Western Design Center, Inc., w65c265s Datasheet - Page 14

• Manufacturer Part Number: w65c265s
• Description: W65c265s 16?bit Microcontroller
• Manufacturer: Western Design Center, Inc.

1.9.2 Asynchronous Receiver Operation
The receiver and its selected control and status functions are enabled when ACSRx5 is set to a "1". The
A receiver interrupt (IRQARx) is generated whenever the receiver shift register is transferred to the receiver
data register.
1.9.3 Asynchronous Control and Status Registers (ACSRx)
The Asynchronous Control and Status Register (ACSRx) enables the Receiver and Transmitter and holds
Bit assignments and function of the ACSRx are as follows:
ACSRx0:
ACSRx1:
Note:
Serial
Data
data format must have a start bit, 7 or 8 data bits, and one stop bit or one parity bit and one
stop bit. The receiver bit period is divided into 16 sub-intervals for internal synchronization.
The receiver bit stream is synchronized by the start bit, and a strobe signal is generated at
the approximate center of each incoming bit. The character assembly process does not start
if the start bit signal is less than one-half the bit time after a low level is detected on the
Receive Data Input. A framing error, parity error or an over-run will set ASCRx7 the receiver
error detection bit. An over-run condition occurs when the receiver data register has not
been read and new data byte is transferred from the receiver shift register.
The receiver requires only one stop bit but the transmitter supplies two stop bits for older
information on communication status error conditions.
Transmitter Enable. The Asynchronous Transmitter is enabled, the Transmitter Interrupt
Transmitter Interrupt Source Select. When ACSRx1=0, the Transmitter Interrupt occurs due
system timing.
Figure 1-9 Asynchronous Data Timing for 7-bit Data without Parity
Start
Bit
(IRQATx), and TXDx is enabled on P61, P63, P65 or P67 when ACSRx0=1.
When ACSRx0 is cleared, the ACSRx1 is cleared, the transmitter will be
disabled, the Transmitter Interrupt will not occur and TXDx will be disabled on
P61, P63, P65 or P67. This bit is cleared by a RESET.
to a Transmitter Data Register Empty condition (end-of-byte transmission).
When ACSR=1 the Transmitter Interrupt occurs due to both the Transmitter
Data and Shift register empty condition (end-of-message transmission). The
Transmitter Interrupt is cleared by writing to the Transmitter Data Register.
0
1
2
3
4
5
6
Parity
Bit
Stop
Bit
14