w65c265s Western Design Center, Inc., w65c265s Datasheet - Page 19

• Manufacturer Part Number: w65c265s
• Description: W65c265s 16?bit Microcontroller
• Manufacturer: Western Design Center, Inc.

1.12
The Processor Defined Cache Control allows the W65C265S to slow its clock rate. The idea of cache with
the W65C265S is that all memory running at the FCLK rate is cache memory. When slower memories are
addressed, the PHI2 clock rate is slowed. PHI2 is slowed by extending the PHI2 low and high times.
Whether or not the clock rate is slowed down is determined by the System Speed Control (SSCR) Register.
7
Processor Defined Cache ControlT
6
Figure 1-14 System Speed Control Register (SSCR)
5
4
CS7B Speed Select
3
0 = Slow
CS6B Speed Select
1 = Fast
0 = Slow
CS5B Speed Select
1 = Fast
System (CS0B-CS7B Speed Select
2
0 = Slow
CS4B Speed Select
1 = Fast
1 = External RAM (00)0000-01FF
0 = Internal RAM (00)0000-01FF
0 = Slow
1 = Fast
0 = Slow (FCLK/4)
1 = Fast (FCLK)
1 = PHI2 Clock source is FCLK/4 or
1
PHI2 System Timing Clock Select
External RAM Select
0 = PHI2 Clock source is CLK
FCLK Start and Stop Control
0
FCLK
1 = Start FCLK
0 = Stop FCLK
SSCRx ($DF41)
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