w65c265s Western Design Center, Inc., w65c265s Datasheet - Page 12

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w65c265s

Manufacturer Part Number
w65c265s
Description
W65c265s 16?bit Microcontroller
Manufacturer
Western Design Center, Inc.
Datasheet
1.8
Timer 3 and 4 provide clock timing for the Asynchronous I/O and establishes the data rate for the Serial I/O
port. Timer 3 and 4 operate as configured by TCRx and TERx (Timer Control Register and Timer Enable
Register) and should be set up prior to enabling the UART.
Table 1-3 identifies the values to be loaded into Timer 3 and 4 to select standard data rates. Although Table
1-3 identifies only the more common data rates, any data rate can be selected by using the formula:
Asynchronous I/O Data Rate Generation (Timer 3 and 4)
FCLK
where N =
16 x bps
N
FCLK
bps
Note:
Baud Rate
Standard
19200
38400
57600
1200
1800
2400
4800
9600
110
150
300
600
decimal value to be loaded in to Timer A using its hexadecimal equivalent
One may notice slight differences between the standard rate and the actual data rate.
However, transmitter and receiver error of 1.5% or less is acceptable.
the clock frequency
The desired data rate
Note: Shading indicates transmitter or receiver error greater than 1.5%.
Table 1-3 Timer 3 and 4 Values for Baud Rate Selection
-------- -
1.8432MHz
$00BF
$02FF
$017F
$005F
$003F
$002F
$000B
$0416
$0017
$0005
$0002
$0001
1
2.4576MHz
$0573
$03FF
$01FF
$00FF
$007F
$0054
$003F
$001F
$000F
$0007
$0003
$0002
3.6864MHz
$082E
$05FF
$02FF
$00BF
$000B
$017F
$007F
$005F
$002F
$0017
$0005
$0003
4.9152MHz
$0AE8
$00AA
$07FF
$03FF
$01FF
$00FF
$003F
$000F
$007F
$001F
$0007
$0004
6.1440MHz
$0DA2
$00DF
$09FF
$04FF
$027F
$013F
$009F
$004F
$0027
$0013
$0009
$0006
12

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