w65c265s Western Design Center, Inc., w65c265s Datasheet - Page 37

• Manufacturer Part Number: w65c265s
• Description: W65c265s 16?bit Microcontroller
• Manufacturer: Western Design Center, Inc.

2.12 Positive Edge Interrupt inputs (PExx)
Port pin P56, P60 and P62 have Positive Edge sensitive interrupt inputs (PE56,PE60,PWM) multiplexed with
the I/O. The associated bit is set (by an internal one-shot circuit) in the Interrupt Flag Register (IFRx) on a
positive transition from "0" to "1". The transition from "1" to "0" has no effect on the IFR. When the
associated Interrupt Enable Register bit (IERx) is set to a "1", the MPU will be interrupted provided the
interrupt flag bit in the MPU status register P (I flag) is cleared to a "0". When the I flag is "1", interrupts are
disabled.
2.13 Negative Edge Interrupt inputs (NExx)
Port pin P57, P62, P64 and P66 have Negative Edge sensitive interrupt inputs (NE57,PWM,NE64,NE66)
multiplexed with the I/O. The associated bit is set (by an internal one-shot circuit) in the Interrupt Flag
Register (IFRx) on a negative transition from "1" to "0". The transition from "0" to "1" has no effect on the
IFR. When the associated Interrupt Enable Register bit (IERx) is set to a "1", the MPU will be interrupted
provided the interrupt flag bit in the MPU status register P (I flag) is cleared to a "0". When the I flag is a "1",
interrupts are disabled.
2.14 Chip Select outputs (active low) (CSxB)
The CSxB Chip Select outputs are enabled (individually) as outputs on Port 7 with the PCS register. Each of
the eight chip selects is dedicated to one block of external memory defined by the programmable chip select
registers; the mapping of each chip select to external addresses is given in Table 1-5, System Memory Map.
2.15 Level Sensitive Interrupt Request input (IRQB)
The I/O function of port pin P41 is multiplexed with IRQB Level Sensitive Interrupt input. When IRQB is held
low the Edge Interrupt Flag Register Bit 7 (EIFR7) is set to a "1". When the Edge Interrupt Enable Register
bit 7 (EIER7) is set to a "1" the MPU will be interrupted provided the I flag of the MPU is cleared to a "0"
allowing interrupts. Unlike the edge interrupts, which do not hold the interrupt bit set, an interrupt will be
generated as long as IRQB is low.
2.16 Non-Maskable Edge and ABORT Interrupt Input (NMIB/ABORTB)
The I/O Function of port pin P40 is multiplexed with both the NMIB edge triggered interrupt and the ABORT
interrupt. When BCR6=1, the NMIB interrupt is enabled; the MPU will be interrupted on all negative edges
of NMIB. Because the I flag cannot prevent NMIB from interrupting, NMIB is thought of as Non-Maskable.
When BCR5=1, the ABORT interrupt is enabled. Should both BCR5 and BCR6 be set to "1", both NMIB
and ABORT are enabled (normally, this is not desirable).
2.17 Asynchronous Receiver Inputs/Transmitter Outputs (RXDx, TXDx)
The W65C265S has four full duplex Universal Asynchronous Receivers and Transmitters (UARTx) that may
be enabled by the Asynchronous Control and Status Registers (ACSRs). When a Receiver is enabled by
ACSRx0=1 then port pin P60, P62, P64 or P66 becomes the Asynchronous Receiver Input (RXDx). When
a Transmitter is enabled by ACSRx4=1, then port pin P61, P63, P65 or P67 becomes the Asynchronous
Transmitter Output (TXDx).
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