m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 88

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

1.12.1
In addition to supporting standard T1/E1 bit rates, the M2852x devices support fractional T1/E1 and DSL rates
from 64 kbps to more than 8.192 Mbps. The actual nominal link rate must be configured through software
parameters.
link rate used for all IMA groups, any link rate within the specified range is possible. A reference clock synchronous
with that link rate must be provided to the device.
For multi-rate applications, internal timing generators (includes the synthesizers) within the device must be
supplied a reference clock with sufficient accuracy and resolution to generate the required bit rates. The following
relationship between link rate and IMA_SysClk frequency exists:
Table 1-20.
As an example, if IMA_SysClk is 49.152 MHz, the link rate boundaries occur at 3.072 Mbps and 6.144 Mbps. The
maximum IMA link rate is given by IMA_SysClk/4, or 12.288 Mbps.
When using the internal bit rate clock generator, the resolution boundaries and maximum link rate are a function of
the “intermediate” frequency (output of the Prescalar) selected. The “intermediate” frequency is a function of the
frequency of the input reference clock (IMA_SysClk or IMA_RefClk) and the resolution of the prescalar (8 bits).
This “intermediate” frequency (INT_FREQ) is limited to IMA_SysClk/16 due to internal synchronization. At this
limit, the values of
IMA_SysClk/16 and the following applies:
Table 1-21.
Returning to the example of IMA_SysClk = 49.152 MHz, if INT_FREQ = 2.56 MHz, then the rate boundaries occur
at 2.56 Mbps and 5.12 Mbps, with a maximum link rate of 10.24 Mbps.
1.12.2
The system designer must select the frequencies of IMA_SysClk and IMA_RefClk such that the IMA core can
process the aggregate cell bandwidth (BW), sample the serial clocks, and the IMA frame rates can be derived.
1.12.2.1
The maximum aggregate cell bandwidth requirement (rule of thumb) is a function of the frequency of IMA_SysClk
and the number of active IMA groups. The following are empirically determined limits when operating with 1 or
more IMA groups:
•
•
28529-DSH-001-K
Link Rate
Link Rate
32 IMA groups:
•
16 IMA groups
•
Maximum Aggregate BW (Mbps) < Frequency of IMA_SysClk (MHz) * (20 / 9).
Maximum Aggregate BW (Mbps) < Frequency of IMA_SysClk (MHz) * (24 / 9).
Section 1.12.2.2
Link Rate Resolution for Variable Rate Applications (direct serial clock)
Link Rate Resolution for Variable Rate Applications (internal bit rate generator)
IMA Link Rates
Link Rate < IMA_SysClk/16
Clock Input Requirements
Aggregate Cell Bandwidth
Table 1-21
Link Rate < INT_FREQ
n x 8 kbps
n x 8 kbps
discusses the input clock requirements. When operating the device with only a single
apply. But it is also likely that the “intermediate” frequency will be lower than
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INT_FREQ < Link Rate < INT_FREQ/2
IMA_SysClk/16 < Link Rate <
IMA_SysClk/8
n x 16 kbps
n x 16 kbps
®
Link Rate > IMA_SysClk/8
Functional Description
Link Rate > INT_FREQ/2
n x 32 kbps
n x 32 kbps
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