m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 22

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

1.1.2.3
Management of the individual links is performed by two state machines: the Transmit Link State Machine and the
Receive Link State Machine. Four possible states are available for each link as shown in
Table 1-3.
The Link State Machines are responsible for handling the transition from one state to another. All functions of the
LSM's are performed internally by the M2852x. Further details are covered in
standard on IMA.
1.1.2.4
The IMA standard provides two options regarding the transmit clocks. The default mode, and most common IMA
application, is Common Transmit Clock (CTC) mode, where all links in the IMA group are generated from the same
source. Thus they are in phase and have the same rate of SICP insertion (1/2049) as the designated TRL link.
The Independent Transmit Clock (ITC) mode is available as an optional feature of the IMA protocol (of course, it is
fully supported by the M2852x family). In this mode, each link runs off of an independent clock at the nominal line
rate. To support these asynchronous links within an IMA group, the rate of SICP insertion is allowed to vary on the
non-TRL links.
The IMA group frame rate for each IMA group must be re-created at the receive end. This regeneration is
necessary to implement the IMA Data Cell Clock and smoothing buffer functionality of the IMA protocol. One
method for generating the Receive IMA group frame rate is to use the line or payload clock recovered from the
receive TRL physical port interface. This clock is a frequency locked reference of the far-end Transmit IMA group
frame rate. Equivalently, the rate of cell transfers (i.e., payload bandwidth) from the TRL link can be used as the
reference for generating the Receive IMA group frame rate. Both methods are available for use by the M2852x
device, depending on the application and configuration.
1.1.2.5
When dealing with multiple facilities, there is no guarantee that the individual links within a group will take the same
physical path between the terminating equipment. This variation is referred to as Differential Delay. The ATM Forum
specification requires an IMA implementation to absorb a minimum of 25 ms of differential delay between the links.
Each link requires 8 K of memory for every 27.5 ms of delay (at E1; 8 K provides for 34.375 ms at T1 rates). The
M28525/9 provides 512K bytes of on-board memory for the buffering necessary to re-align the links within an IMA
group. This is sufficient to support the 50 ms of delay (at E1 rates) for 32 IMA ports. In addition, an external
memory bus allows this to be expanded to 2 MB, which supports up to 200 ms of delay.
memory requirements for differential delay.
28529-DSH-001-K
Not in Group
Unusable
Usable
Active
Link States
Link State Machine
Transmit Clocks
Differential Delay
State
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the link is in a group but cannot be used due to line fault etc.
assigned to a group and ready but is waiting for the other end
fully configured and carrying traffic
this link has not been added to an IMA group
®
Description
Section 1.12
Functional Description
Table 1-4
Table
and in the ATM
1-3.
shows the
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