m28529-12 Mindspeed Technologies, m28529-12 Datasheet - Page 112

• Manufacturer Part Number: m28529-12
• Description: Inverse Multiplexing For Atm Ima Family
• Manufacturer: Mindspeed Technologies

Figure 1-31. CN8370 Interface - E1 Timing Diagram
1.14.2.5.2
The purpose of the fractional T1/E1 logic is to gate off the serial clocks during inactive timeslots. The fractional T1/
E1 logic is enabled on a link-by-link basis when in serial mode or on all four links when the interleaved highway
mode is enabled.
Figure 1-32
input is used to indicate active data timeslots. The clocks are gapped internally in the M28525/9 during inactive
timeslots. ATM cell bytes are continuously mapped into active timeslots.
28529-DSH-001-K
Tx Framer Marker
Rx Framer Marker
2.048 MHz Clock
shows an example of fractional T1 timing. In this mode, the clock frequency is 1.544 MHz and the sync
General Notes:
Tx Serial Data
T1 Mod Count
Rx Serial Data
T1 Mod Count
In E1 mode, ATM Cells are mapped inot time slots 1-15 and 17-31 as described in recommendation G.804.
Fractional T1/E1 Interface
TS31
TS31
LSB
LSB
0
0
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MSB
255
MSB
255
TS0
TS0
®
Functional Description
97